Introduction to Silicon Programming in the Tangram/Haste language

1
Introduction to Silicon Programmingin the
Tangram/Haste language

• Material adapted from lectures by
• Prof.dr.ir Kees van Berkel
• Dr. Johan Lukkien
• Dr.ir. Ad Peeters
• at the Technical University of Eindhoven, the
  Netherlands

2
Handshake protocol

• Handshake between active and passive partner
• Communication is by means of alternating request
  (from active to passive) and acknowledge (from
  passive to active) signals
• Active send request, then wait for acknowledge
• Passive wait for request, then send acknowledge

Active
Passive
3
Handshake component sequencer
Master
Task 1
Task 2
4
Four-phase handshake protocol

• Circuit level implementation has separate wires
  for request and acknowledge
• Four-phase handshake protocol implements
  return-to-zero of these wires

Active Side Req 1 Wait (Ack) Req 0
Wait (-Ack)
Passive Side Wait (Req) Ack 1 Wait
(-Req) Ack 0
Req
Ack
5
Handshake signaling
event sequence ar? ak? ar? ak?
6
Handshake behaviors

• Let xi be boolean variables, and Si commands
• skip always terminates without effect
• x? is a shorthand for x true and x? for x
  false
• S1 S2 denotes sequential execution of S1 and
  S2
• S1 S2 denotes parallel execution of S1 and S2
• Program notation inspired by Martin.

7
Handshake behaviors

• Let Gi be boolean expressions.
• Selection G1 ? S1 GN ? SN
  execute an arbitrary Si for which guard Gi
  holds. When no guard holds then suspend
  execution until otherwise.
• Repetition ?G1 ? S1 GN ? SN
  repeatedly execute Si for which Gi holds until
  all guards are false.

8
Useful shorthands

• wait until G G ? skip
• Note G S G ? S
• Unbounded repetition ?S ?true ? S

9
Useful shorthands

• Four-phase handshakes
• a? ar ak? ?ar ak?
• a? ar? ak ar? ?ak
• Two-phase handshakes
• a?? ar ak?
• a?? ?ar ak?
• a?? ar? ak
• a?? ar? ?ak

10
Reorder properties

• In the absence of timing assumptions,
• One cannot observe the order of output
  transitions
• x1? x2?
• x2? x1?
• x1? x2?
• One cannot fix the order of input transitions
• x1 x2 x2 x1 x1
  x2 x1 ? x2

11
Enclosure and properties

• Enclosure
• a?? S ar S ak?
• a?? S ? ar S ak?
• Reorder property
• a?? b??
• ar (br bk?) ak?
• br (ar ak?) bk?
• b?? a??

12
Decomposition rule

• Let program P S and let a be a
  fresh channel
• Program P can be decomposed into two parallel
  processes P a?? a?? and
  ?a?? S a??

13
Some handshake components

• Repeater a?? ?b?? b??
• Mixer ? a?? c?? a?? c?? b??
  c?? b?? c??
• Sequencer ?a?? (b?? b?? c??)
  a?? c??

a
14
Handshake circuit duplicator

• For each handshake on a0? the duplicator produces
  two handshakes on a1?
• ?a0?? (a1?? a1?? a1??) a0?? a1??
• cf. Handshake behavior sequencer.

15
Production rules

• Production rules are guarded commands that
  specify (CMOS) gates
• ? F ? z?, G ? z? ?
• Interpretation
• do F then ztrue or G then zfalse od
• Guards must be mutually exclusive (environment)
• A gate is combinational if F ? G is a tautology
  and it is sequential (state-holding) otherwise
• Guards must be stable once a guard is true it
  must remain true until completion of transition

16
Behavior of a gate network

• Gate network is the union of all pairs of
  production rules (gates)
• The concurrent execution of this set of PRs
  amounts to Martin
• ? select a PR fire that PR
• If guard of PR equals false, firing skip
• (firing a PR is an atomic action)

17
Initializable

• A handshake component realization is
  initializable
• when all inputs are false, the gate network must
  autonomously proceed to an initial state
• when all passive inputs are false, the component
  must autonomously proceed to a state with all
  active outputs false.

18
Handshake components realization

• From handshake notation to gate network in 8
  steps
• Specify component in handshake notation.
• Expand to individual boolean variables (wires).
• Introduce auxiliary state variables (if
  required).
• Derive a set of production rules that implements
  this refined specification.
• Make production rules more symmetric (cheaper).
• (Verify isochronic forks.)
• Verify initialization constraints.
• Analyze time, area, and energy.

19
For those who are interested in the details

• Synthesis of Asynchronous VLSI Circuits
• Alain J. Martin
• Caltech CS-TR-93-28
• PostScript link via async.bib (html version)
• Programming in VLSI From communicating processes
  to delay-insensitive circuits
• Pages 164 in C.A.R. Hoare, ed.,
• Developments in Concurrency and Communication

20
Handshake components realizations

• Connector trivial
• Repeater alternative symmetrizations
• Mixer isochronic forks
• Sequencer introduction of auxiliary variable
• Duplicator up to you?
• Selector up to you!

21
Connector realization
a

• Behavior ?a?? b?? a?? b??
• Expansion
• ? ar br? bk ak? ?ar br?
  ?bk ak?
• Production rules
• bk ? ak? ar ? br?
• ?bk ? ak? ?ar ? br?
• A pair of wires (!) no area, no delay, no
  energy.

b
22
Repeater realization

• Behavior a?? ?b?? b??
• Expansion
• ar ? br? bk br? ?bk ak?
• Production rules
• false ? ak? ar ? ?bk ? br?
• true ? ak? bk ? br?
• However, not initializable!

23
Repeater realizations
24
Repeater area, delay, energy

• Repeater area, delay, energy
• Area 2 gate equivalents
• Delay per cycle 2 gate delays
• Energy per cycle 2 transitions

25
Mixer realization
a
b

• Behavior ? a?? c?? a?? c??
  b?? c?? b?? c??
• Restriction ?ar ? ?br must hold at all times!
• Expansion
• ? ar cr? ck ak? ?ar cr?
  ?ck ak?
• br cr? ck bk? ?br cr?
  ?ck bk?

c
26
Mixer realization

• Production rules
• ar ? ck ? ak? br ? ck ? bk? ?ck ? ak?
  ?ck ? bk?
• ar ? br ? cr? ?ar ? ?br ?
  cr?
• More symmetric production rules
• ar ? ck ? ak? ar ? ck ? ak?
  
• ?ar ? ?ck ? ak? ?ar ? ?ck ? ak?
• premature ak? more expensive

27
Mixer realizations

• Mixer area, delay, energy
• Area 6 gate equivalents
• Delay per cycle 8 gate delays
• Energy per cycle 8 transitions

28
Duplicator chains

• Assume aM toggles at frequency f.
• Hence a0 toggles at frequency f / 2M.
• Let Edup be the duplication energy per cycle.
• Power of duplicator chain equalsP f Edup
  (1/2 1/4 1/8 ...) lt f Edup

29
Join realization

• Behavior ? a?? b?? c?? a??
  b?? c??
• Expansion ? ar br cr?
  ck bk? ak? ?ar ?br cr?
  ?ck bk? ak?
• ? ar ? br cr? ck
  bk? , ak? ?ar??br cr? ?ck bk? ,
  ak?

30
Join realization

• ar ? br cr? ck bk? , ak?
  ?ar??br cr? ?ck bk? , ak?
• Production rules ck ? ak?
  ck ? bk??ck ? ak? ?ck? bk? ar ? br
  ? cr? ?ar ? ?br ? cr?

31
Join realization

• ck ? ak? ck? bk? ?ck ? ak?
  ?ck? bk?
• ar ? br ? cr? ?ar ? ?br ?
  cr?
• Join area, delay, energy
• Area 2 gate equivalents
• Delay per cycle 4 gate delays
• Energy per cycle 4 transitions

32
Sequencer realization

• Specification ?(a?? (b?? b?? c??) )
  (a?? c??)
• Expansion ? ar br? bk br? ?bk
  cr? ck ak? ?ar cr? ?ck
  ak?

33
Sequencer realization

• Sequencer area, delay, energy
• Area 5 gate equivalents
• Delay per cycle 12 gate delays (8 with optimized
  C-element)
• Energy per cycle 12 transitions (10 with
  optimized C-element)

34
Parallel realization

• ? a?? ((b?? b??) (c?? c??)) a??
• Cf. Join component
• Expansion ? ar ( (br? bk br?
  ?bk) (cr? ck cr?
  ?ck) ) ak? ?ar ak?

35
Selector (specification)

• ? (a?? b?? x? b?? d??
  c?? x? c?? e?? )
  (a?? x ? d?? ? x ? e?? )

36
Assignment duplicator realization

• Behavior ?a?? (b?? b?? b??)
  a?? b??
• Required realization with 2 sequential
  gates(sequencer mixer requires 3 sequential
  gates)
• Follow all 8 realization steps!!
• Add comparison with sequencermixer realization.