Combinational

1
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Clock
j
l
m
k
0x000 irmovl 0x100,ebx ebx lt-- 0x100
Cycle 1
0x006 irmovl 0x200,edx edx lt-- 0x200
Cycle 2
0x00c addl edx,ebx ebx lt-- 0x300 CC
lt-- 000
Cycle 3
0x00e je dest Not taken
Cycle 4
0x013 rmmovl ebx,0(edx) M0x200 lt-- 0x300
Cycle 5
j Beginning of cycle 3
k End of cycle 3
Combinational Logic
Combinational Logic
Data memory
Data memory
CC 100
CC 100
Read Ports
Write Ports
Read Ports
Write Ports
000
Register file ebx 0x100
Register file ebx 0x100
ebx lt-- 0x300
0x00e
PC 0x00c
PC 0x00c
l Beginning of cycle 4
m End of cycle 4
Combinational Logic
Combinational Logic
Data memory
Data memory
CC 000
CC 000
Read Ports
Write Ports
Read Ports
Write Ports
Register file ebx 0x300
Register file ebx 0x300
0x013
PC 0x00e
PC 0x00e