Appendix B.5: Constructing a Basic Arithmetic Logic Unit (ALU)

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Appendix B.5: Constructing a Basic Arithmetic Logic Unit (ALU)

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Constructing a Basic Arithmetic Logic Unit ... 01 add 0 10 sub 1 10 slt 1 11 MIPS ALU Most-significant bit Function Bnegate Operation and ... Architecture Subject ... –

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Title: Appendix B.5: Constructing a Basic Arithmetic Logic Unit (ALU)

1
Appendix B.5 Constructing a Basic Arithmetic
LogicUnit (ALU)

Dr. Gheith Abandah
Adapted from the slides of Professor Mary Irwin
(www.cse.psu.edu/mji) which in turn Adapted from
Computer Organization and Design,
Patterson Hennessy

2
MIPS Number Representations

32-bit signed numbers (2s complement)0000
0000 0000 0000 0000 0000 0000 0000two 0ten0000
0000 0000 0000 0000 0000 0000 0001two
1ten...
0111 1111 1111 1111 1111 1111 1111 1110two
2,147,483,646ten0111 1111 1111 1111 1111 1111
1111 1111two 2,147,483,647ten1000 0000 0000
0000 0000 0000 0000 0000two
2,147,483,648ten1000 0000 0000 0000 0000 0000
0000 0001two 2,147,483,647ten...
1111 1111 1111 1111 1111 1111 1111 1110two
2ten1111 1111 1111 1111 1111 1111 1111 1111two
1ten

Converting lt32-bit values into 32-bit values
copy the most significant bit (the sign bit) into
the empty bits 0010 -gt 0000 0010 1010 -gt
1111 1010
sign extend versus zero extend (lb vs.
lbu)

3
MIPS Arithmetic Logic Unit (ALU)

Must support the Arithmetic/Logic
operations of the ISA
add, addi, addiu, addu
sub, subu, neg
mult, multu, div, divu
sqrt
and, andi, nor, or, ori, xor, xori
beq, bne, slt, slti, sltiu, sltu

With special handling for
sign extend addi, addiu andi, ori, xori, slti,
sltiu
zero extend lbu, addiu, sltiu
no overflow detected addu, addiu, subu, multu,
divu, sltiu, sltu

4
Review 2s Complement Binary Representation
2sc binary decimal
1000 -8
1001 -7
1010 -6
1011 -5
1100 -4
1101 -3
1110 -2
1111 -1
0000 0
0001 1
0010 2
0011 3
0100 4
0101 5
0110 6
0111 7
-23
-(23 - 1)

Negate

Note negate and invert are different!

23 - 1
5
Binary Addition
6
Review A Full Adder
carry_in
A B carry_in carry_out S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
A
1-bit Full Adder
S
B
carry_out

S A ? B ? carry_in (odd parity
function)
carry_out AB Acarry_in
Bcarry_in
(majority function)

How can we use it to build a 32-bit adder?
How can we modify it easily to build an
adder/subtractor?

7
A 32-bit Ripple Carry Adder/Subtractor

Remember 2s complement is just
complement all the bits
add a 1 in the least significant bit

A 0111 ? 0111
B - 0110 ?
1001
1
0001
1 0001
8
Overflow Detection

Overflow the result is too large to represent
in 32 bits
Overflow occurs when
adding two positives yields a negative
or, adding two negatives gives a positive
or, subtract a negative from a positive gives a
negative
or, subtract a positive from a negative gives a
positive
On your own Prove you can detect overflow by
Carry into MSB xor Carry out of MSB, ex for 4 bit
signed numbers

1
1
6
7
9
Tailoring the ALU to the MIPS ISA

Need to support the logic operations
(and,nor,or,xor)
Bit wise operations (no carry operation involved)
Need a logic gate for each function, mux to
choose the output
Need to support the set-on-less-than instruction
(slt)
Use subtraction to determine if (a b) lt 0
(implies a lt b)
Copy the sign bit into the low order bit of the
result, set remaining result bits to 0
Need to support test for equality (bne, beq)
Again use subtraction (a - b) 0 implies a b
Additional logic to nor all result bits
together
Immediates are sign extended outside the ALU with
wiring (i.e., no logic needed)