COE%201502%20Memory%20Model

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COE 1502Memory Model
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Introduction

• Our current processor uses a memory interface
  with the assumptions
• Interface signals
• MemRead, MemWrite, MemoryAddress, MemoryDataOut
• MemWait, MemoryDataIn
• Byte-addressed
• Handshaking bus protocol (for reads)

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Introduction

• However, the SRAM memory on the Wild-One board
• Word addressed
• Different set of interface signals
• Different bus protocol
• It uses a bus arbitration protocol
• The goal of this unit is to reconcile these
  differences and use this memory for our processor
• For simulation, we have provided a VHDL model for
  the memory
• When we load our processors onto the FPGAs, well
  remove the model and use the real memory

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Introduction

• Wild-One card has two FPGAs that may desire to
  use the memory (32K x 32 SRAM)
• Memory bus consists of an address bus (24-bit)
  and two data buses (32-bit)
• Control signals are used by the FPGAs to gain
  access to the bus (become bus master)

Shared bus
Local control
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Interfacing your CPU to Memory on the Wildfire
Board
Simulator memory model from COELib
Parts you will design BUS CONTOLLER LOGIC
DATA ALIGNMENT UNIT
Your current CPU Design
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Bus Arbitration

• In order to use the memory on the Wild-One card,
  we use centralized bus arbitration
• Control signals
• MemBusReq_n, MemStrobe_n, MemWriteSel_n
• MemBusGrant_n
• Data signals
• MemAddr_OutReg, MemData_OutReg
• MemData_InReg
• A bus controller will reconcile the differences
  between the existing handshaking protocol and
  this protocol
• Uses the MemWait signal to stall the processor
  while arbitration is being performed on behalf of
  the processor

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Memory Read
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Memory Write
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Bus Arbitration

• We use a bus for the processor to access the
  memory
• A bus is a shared communication link
• How is the bus reserved by a device that wishes
  it to communicate?
• Single Master
• CPU is master, memory/(all others) is slave (we
  assumed this before)
• Arbitration schemes
• Multiple bus master system
• Arbiter decides who is the bus master
• Arbiter may employ priority

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Bus Arbitration

• Bus arbitration schemes (control signals shown)

• Daisy chain

• Centralized, parallel

• Distributed by collision detection

• Distributed by self-selection

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Word Alignment

• The next problem we must solve
• MemAddr_OutReg is word aligned
• Address bits 1 and 0 are not used
• Must do something about LH and LB which do not
  address the low-order portion of the word
• Solution use little-endian addressing

Half words within word
Bytes within word
Byte offset within word Byte offset within word
10 00
Byte offset within word Byte offset within word Byte offset within word Byte offset within word
11 10 01 00
Because the processor sign/zero-extends the
low-order portion of the word on a LH, LHU, LB,
LBU, we just need to right-shift the contents
depending on the offset! Note this has
implications for stores!
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Alignment Unit

• Three modes for the alignment unit
• Word mode pass all data, unshifted
• Halfword mode shift top two byte lanes to low
  two byte lane (if offset 10)
• Byte mode shift high byte lanes to low order
  (dep. on offset)

Address(0) Address(1)
CPU will Sign extend if necessary
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Note! YOU MUST DO THIS FOR MEMORY CODE TO WORK

• Must make sure you set