CSE 246: Computer Arithmetic Algorithms and Hardware Design

1
CSE 246 Computer Arithmetic Algorithms and
Hardware Design
Lecture 4

• Instructor
• Prof. Chung-Kuan Cheng

2
HW 2 Due 1/27/05

• 11.2, 11.6, 11.7
• Design a number system different from the
  conventional binary system. Inventing a new
  number system would be ideal. Show that the
  number system is better than the binary system in
  certain aspect/s. Also, design/describe the basic
  operations such as addition, subtraction, and
  comparison.

3
Topics

• Adders
• Synchronous v.s. Asynchronous
• AND/OR gate v.s. Circuit
• Logic angle
• Graph angle (Prefix Adder)

4
Prefix Computation

• FSM example
• Given
• initial state S0A
• A sequence of inputs (0 0 1 1 1 0 1 0 1)
• Derive the sequence of outputs

PS NS12
A B
B B
C B
Compute Ns N1M0 N2M0 M0 N3M1 M0 M0 N4M1 M1
M0 M0
PS NS13
A C
B C
C C
Input Sequence 0 0 1 1
State table
PS Next State
X0 X1
A B A
B B C
C B A
PS NS14
A A
B A
C A
5
Graph Based Approach

• Consider the (g p) chain
• break the long paths

g3
p3
g2
p2
C4
g1
p1
C1
6
Graph Based Approach

• Generating g32 and p32

g3
g2
p3
p2
g1
p1
C4
g3
p3
g2
p2
C1
g32
p32
7
Graph Based Approach

• Generating g10 and p10

g3
g2
p3
p2
g1
p1
C4
g1
p1
cin
cin
g10
p10
8
Graph Based Approach

• Generating g30 and p30

g32
p32
g10
g30
p10
p30
9
Boolean Approach

• g4 p4 ( g3 p3 ( g2 p2 ( g1 p1 ( g0 p0
  cin ) ) ) )
• g4 , p4 g3 , p3 g2 , p2 g1 , p1 g0
  , p0 cin
• g4p4g3 , p4p3 g2p2g1 , p2p1 g0
  , p0cin
• g4p4g3p4p3(g2p2g1) , p4p3p2p1 g0 ,
  p0cin
• g4p4g3p4p3(g2p2g1)(p4p3p2p1)g0 , (p4p3p2p1)
  p0cin

10
Prefix Adder

• Given
• n inputs (gi, pi)
• An operation o
• Compute
• yi (gi, pi) o o (g1, p1) ( 1 lt i lt n)

• Associativity
• (A o B) o C A o ( B o C)

a, i1 aibi , otherwise 1, i1 ai xor bi ,
otherwise
gi pi

• (g, p) o (g, p) (g, p)
• gg pg
• ppp

11
Prefix Adder Graph Representation
ai bi

• Example
• Ripple Carry Adder

(gi , pi)
x y
xoy xoy
12
Prefix Adders Conditional Sum Adder
8 7 6 5 4 3 2 1
13
Prefix Adders Conditional Sum Adder
8 7 6 5 4 3 2 1

• alphabetical tree
• Binary tree
• Edges do not cross

• For output yi, there is an alphabetical tree
  covering inputs (xi, xi-1, , x1)

14
Prefix Adders Conditional Sum Adder
8 7 6 5 4 3 2 1

• The nodes in this tree can be reduced to
• (g, p) o c gpc

• From input x1, there is a tree covering all
  outputs (yi, yi-1, , y1)

15
Prefix Adders size and depth

• Objective
• Minimize of nodes, sc(n).
• Minimize depth, dc(n)
• Ripple Carry Adder
• sc(8) 7
• dc(8) 7
• total 14
• Conditional Sum Adder
• sc(8) 12
• dc(8) 3
• total 15

16
Prefix Adders size and depth

• Theoremsc(n)dnc(n) gt sc(n)dnc(n) gt 2n-2
• dnc(n) means the depth of the last output
• Proof
• Alphabetical tree of yn contains n-1 internal
  nodes.
• For each column where the prefix is not ready,
  at lease one extra node is needed, therefore we
  need at least n-(dnc(n) 1) extra nodes
• sc(n) gtn-1(n(dnc(n)1))2n-2-dnc(n)
• sc(n) dnc(n) gt 2n-2

17
Prefix Adders Brent Kung Adder
15 14 13 12 11 10 9 8 7 6 5 4 3
2 1 0

• sc(16) 26
• dc(16) 6
• total 32

18
Carry Skip Adder
a3,0 b3,0
a7,4 b7,4
a11,8 b11,8
cin
c4
c8
c12
A0
A1
A2
p3,0
p7,4
p11,8
x
0 1
0 1
0 1
c12
c4
c8

• If p3,0p3p2p1p0 1, then x cin

19
Carry Propagation Paths

• A2 lt- MUX lt- MUX lt- cin
• A2 lt- MUX lt- A1
• A2 lt- MUX lt- MUX lt- A0
• c12 lt- MUX lt- A2
• c12 lt- MUX lt- MUX lt- A1
• c12 lt- MUX lt- MUX lt- MUX lt- A0
• c12 lt- MUX lt- MUX lt- MUX lt- MUX lt- cin

20
False Path

• A1 lt- MUX lt- A0 lt- cin is a false path
• If carry is from cin, then block must have
  p3p2p1p0 1
• Since p3,0 1, g3,0 must be 0
• The carry is not generated from A0
• The carry needs not to propagate via A0, it will
  go from the MUX

21
Label Algorithm

• Problem
• Given a digraph, a set of false paths
• Derive the longest path of the graph
• Algorithm
• Color the edges on each false path a label
• The length of the walk of the same labels are
  accumulated
• Otherwise, change to no label