ver 1.0

1
Layout Design and Verifications on Diva

• Cross Section Layout View
• Layout (Design) Rules
• Cell Butting Rules
• Edit Layout
• Verifications (DRC/LVS)
• Create Abstract

2
Cross Section Layout View
3
Definition For Parameters Of Layout Rules
???? (Definition)
1.?????????? 2.??????? layout rules ??????, ??
layout ??????????
4
Layout (Design) Rules (I)
1. NW (N well)
?? NW??? ????? NW ???????, ??????? ???????
??? NW ?????, ??? Metal 1 ??????
???um
5
Layout (Design) Rules (II)
2. OD (thin oxide)
???um
6
Layout (Design) Rules (III)
3. PO (Poly)
3.c
???um
7
Layout (Design) Rules (IV)
4. PP(P implantation) NP(N implantation)
???um
8
Layout (Design) Rules (V)
5. CO (contact)
???um
9
Layout (Design) Rules (VI)
6. M1 (Metal 1)
???um
10
Layout (Design) Rules (VII)
7. VIA (VIA 1)
???um
11
Layout (Design) Rules (VIII)
8. M2 (Metal 2)
???um
12
Layout (Design) Rules (IX)
9. VIA 2
???um
13
Layout (Design) Rules (X)
10. M3 (Metal 3)
???um
14
Cell Butting Rules (A)

• ????? 0.6um Single Poly Double
• Metal ?????? Standard Cell ??
• ???CMOS ???????????
• ????????????? Cell ?
• ????,????? Design Rule?
• ?????????,????
• pitch(2.4um) ???,?? Cell ???
• ?????,????????,??
• ??? pitch ????
• ????? pitch????? pin??
• ??????????
• ???(VSS/Metal 1) ????????
• ?? layout ?????????(0,0)?
• VDD?VSS ??? Metal 1 ?????
• ???????????(exp.,21.2um)
• ?????? 0.9 ? 0.9Mini ????
• ????? 0.9um,? 1.2Max ???
• ??????? 1.2um?

15
Example Using Cell Butting Rules (A)
16
Cell Butting Rules (B)

• ????? 0.6um Single Poly Double
• Metal ?????? Standard Cell ??
• ??? CMOS ???????????
• ????????????? Cell ?
• ????,?????Design Rule?
• ?????????,????
• pitch(2.3um) ???,?? Cell ???
• ?????,????????,??
• ??? pitch ????
• ????? pitch ????? pin??
• ??????????
• ???(VSS/Metal 1) ????????
• ?? layout ?????????(0,0)?
• VDD?VDDL?VSS ??? Metal 1 ?
• ???????????????
• (exp.,34um)
• ?????? 0.9Min ???????
• ?? 0.9um,? 1.2Max ??????
• ???? 1.2um?

17
Example Using Cell Butting Rules (B)
18
Create Layout View
19
Edit Layout
???command
???? Library Browser ? Adder4-gt and5 -gt
layout ??????? Edit ????????
?????????
?????
???? ??CIW ???
?? LSW(Layer Selection Window) ?????Edit??
????? ????
??LSW ???? ???
???????? ?????
??????
?? instance, pin ?? ???
library name
?????? ?????? ????
?????????? ?,????? hot key, ???????? Shift ? ???
Ctrl ????
LSW??? ?????
?????? ?????? ??????
??????????k ?,??????K??
LSW???? ??????
20
Compare Layers
?? Technology file ????? Layer name ? Layout
rule ?? Layer name ??????
??,? Technology file ???????? Layer name ??????
Layer number ??? Layer name ?? dg(drawing) ?
pn(pin) ?????????,? ????? purpose??? ??,?dg
?252,?pn ? 251? ??? Layout ??? dg ?,??????pin
? ???? pn?
NW (N Well) OD (thin oxide) PP (P
implantation) NP(N implantation) PO (poly) M1
(metal 1) VIA (VIA 1) CO (contact) M2 (metal 2)
21
Set Grid
22
Start Layout
??? schematic ? ?,??? layout, ???????? ???,???? ??
( symbolic diagram ),??? ?????,?? ?????,?? ?????
pitch ?.
?? pitch ?? ?????? ?????? pin???and5 ,?? 6
??? ? pin,? layout ?????? ? 6 ? pitch ? ,??????.
23
Practice Layout (I)
24
Practice Layout (II)
25
Practice Layout (III)
???????????,?? via ? contact ???????????, ??????
poly ??,?? metal 2 ???????
(contact)
(poly)
(metal 1)
(poly ? metal 1)
(via)
(poly ? metal 1)
(metal 2)

• (poly ? metal 2)
• contact ? via ????

(poly ? metal 2)
(poly ? metal 2 ??? pin)
(pin)
poly ??
metal 2 ? pin ??
26
Practice Layout (IV)
27
Practice Layout (V)
28
Practice Layout (VII)
29
Finished Layout

• ??????
• ??? pin ???? cell ??
• ?? pin ?????????
• ???? pitch
• ?????? pin????
• boundary ?????????
• pitch
• ??? Feedthrough pin
• ??? WELL contact
• pmos ? nmos ? drain ??
• layout ??????,??
• ?????

30
Verifications

• Ckt layout ???????????
• DRC (Design Rule Check)
• ? IC ???(layout) ??????????????
• ?????????????
• ERC (Electrical Rule Check)
• ?? power, ground ? short, floating device,
  floating net
• ?????????
• LVS (Layout Versus Schematic)
• ? layout ? schematic ???,????????,?
• MOS ? Length?Width ?????
• LPE (Layout Parameter Extarction)
• ? layout database extract ???? (? MOS ? W?L ?
• ,BJT,diode ? area,perimeter,node ? parastic
  cap.)
• ,?? HSPICE netlist ???????

31
Diva Versus Dracula

• ?????? IC ??????????,??????????
• ???????,???????? DRC( Design Rule Check),
• ERC(Electric Rule Check) ? LVS(Layout vs.
  Schematic ???)?
• Cadence ?????????
• Opus ?? Diva ? on-line ???,??????? cell ?
• ? Opus ???????,???????????????
• ?,?????,Diva ? run time ? Dracula ??
• Dracula ??? batch-job ??,Dracula (???) ??????
• ?????,??????? IC ??????? sign-off ?
• ???
• ?? Diva ???? cell ??? block ? layout ????,?
• whole chip ??????????? Dracula ???

32
Diva DRC (I)
33
Diva DRC (II)
34
Create Extracted View
35
Diva LVS (I)
36
Diva LVS (II)
37
Create Abstract View (I)
38
Create Abstract View (II)
39
Abstract View Change Property (I)
40
Abstract View Change Property (II)
41
Abstract View Change Property (III)