EGR 277

1
Lecture 14 EGR 277 Digital Logic
Reading Assignment Chapter 5 in Digital Design,
3rd Edition by Mano
Self-starting counters Counters are considered
to be self-starting if all unused counts
eventually lead to the correct counting sequence.
Since the initial state for a flip-flop is
unpredictable upon powering up the IC, a counter
that is not self-starting could possibly power up
into an unused state that would not eventually go
into the correct counting sequence (so the
counter might lock up in an incorrect count or
counting pattern. Recall that the next states
for unused counts were sometimes treated as
dont cares. With this method it is difficult
to predict what will happen if the counter powers
up into an unused count (although it can be later
determined by analyzing the circuit). A safer
technique it to let all unused counts have a
valid count for their next state.
2
Lecture 14 EGR 277 Digital Logic
Example Consider the state diagrams for two
modulo-5 counters below. Are they self-starting?
Case 1 Counter is NOT self-starting. Next
states for unused counts 5, 6, and 7 were perhaps
treated as dont cares.
Case 2 Counter is self-starting. Next states
for unused counts 5, 6, and 7 were all set to
count 0.
3
Lecture 14 EGR 277 Digital Logic
Example Determine the counting sequence for the
counter shown (begin with count 0). Use a timing
diagram to display the values of Clock, JA, KA,
JB, KB, JC, KC, A, B, and C. Is the counter
self-starting?
4
Lecture 14 EGR 277 Digital Logic
State Reduction In some sequential circuits, the
numeric values of the states is not
important. Perhaps the circuit simply needs to
produce a certain output sequence. As long as
the output sequence is correct, then if we can
reduce the number of states (and thus the number
of flip-flops), then the final circuit can be
simplified. Shown below are examples of such
circuits.
Note Reducing the number of states may not
always reduce the number of flip-flops. For
example, if the number of states is reduced from
13 to 9, then 4 flip-flops are still required.
However, the associated combinational logic
circuitry may be reduced.
5
Lecture 14 EGR 277 Digital Logic
State Reduction Procedure 1) Form the state
table. 2) If 2 states are equivalent, eliminate
one and replace all references to it with the
equivalent state. Note Two states are
equivalent if for each input combination they
give identical outputs and have the same next
state or an equivalent next state. 3) Redraw the
state table. Repeat steps 2 and 3 as many times
as possible. 4) Draw the final (reduced) state
diagram. 5) Test the original and reduced state
diagrams to insure that they produce the same
result.
6
Lecture 14 EGR 277 Digital Logic
Example (reference Digital Design, by Mano,
p. 199) Use state reduction to reduce the state
diagram below if possible. Draw the reduced
state diagram.Test the original state diagram and
the reduced state diagram with the input sequence
01010110100 to see if they produce the same
output sequence.
7
Lecture 14 EGR 277 Digital Logic
Example (continued) Test the original state
diagram and the reduced state diagram with the
input sequence 01010110100 to see if they produce
the same output sequence.
Original state diagram
Reduced state diagram
8
Lecture 14 EGR 277 Digital Logic
Sequence Detector An example of a circuit whose
output sequence is critical and the numeric value
of the states is unimportant is a sequence
detector. Such a circuit might be used to
detect a certain bit pattern (such as in
synchronizing two signals) or for a digital lock
where the lock is unlocked when a correct
combination (sequence) is entered.
Example Design a sequence detector to detect
the sequence 1010. The sequence detector should
also detect overlapping sequences. The circuit
should output a binary 1 when a valid sequence is
detected.
9
Lecture 14 EGR 277 Digital Logic
Example (continued) Use state reduction on the
last example to see if the number of states can
be reduced. If so, draw the new state diagram
and discuss how it differs from the original
design.
10
Lecture 14 EGR 277 Digital Logic
Example (continued) Test the original state
diagram and the reduced state diagram with the
input sequence 0101011001010100 to see if they
produce the same output sequence.
Original state diagram
Reduced state diagram
11
Lecture 14 EGR 277 Digital Logic
Example (Problem 5-17 from Digital Design, 3rd
Edition, by Mano) Design a one input, one output
serial 2s complementer. The circuit accepts a
string of bits from the input and generates the
2s complement at the output. The circuit can be
reset asynchronously to start and stop the
operation.