Graphical User Interface for Reconfigurable Processor

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Graphical Design Environment for a Reconfigurable
Processor
Tu Le Institute of Advanced Microelectronics ECE/C
AMBR University of Idaho le7775_at_uidaho.edu
David M. Buehler Institute of Advanced
Microelectronics ECE/CAMBR University of
Idaho dbuehler_at_uidaho.edu
Gregory Donohoe Institute of Advanced
Microelectronics ECE/CAMBR University of
Idaho donohoe_at_cambr.uidaho.edu
Pen-Shu Yeh NASA GSFC Code 567 pen-shu.yeh_at_gsfc.na
sa.gov
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Overview

• Field Programmable Processor Array (FPPA)
• Graphical Programming
• FPPA Matlab Simulink model (floating point)
• FPPA graphical interface design flow
• Examples
• Summary
• Future work

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Field Programmable Processor Array (FPPA)

• An embedded data processor VLSI chip for
  spacecraft.
• Radiation-tolerant, 0.25m CMOS process
• 16 on-board, fixed point processing elements
• Implements a reconfigurable synchronous data
  flow processor
• Run-time reconfigurable
• Extensible by tiling multiple chips
• Serves as accelerator to a host CPU
• Application development
• Text base development
• Configuration and Run-time compilers
• Standalone functional simulator
• FPPA Simulink graphical design environment (GUI)

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FPPA Data Path Elements

• FPPA features
• 16 configurable on-board PEs
• Four 16-bit-wide, bidirectional I/O ports
• One 16-bit-wide dedicated output port
• On-board program memory and execution unit
• Interface control signals

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Processing Element (PE) components
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Example of the simple pipeline using multiple
PEs
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FPPA programming complexity

• Data path descriptions
• PE
• Cluster
• I/O
• Runtime descriptions
• Enable / Disable PEs
• External peripherals
• Procedural languages like C do not naturally
  describe a dataflow architecture like the FPPA

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Realizing 4 taps FIR filter with FPPA
Data Path
Difference Equation
Routing of output and local bus data
Routing of input data
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Graphical Programming

• Naturally represents dataflow computational model
• Quick to learn
• Familiar Matlab Simulink graphical design
  environment
• Floating point versus Fixed point implementation
• Rapid Development and Validation

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FPPA Simulink Model

• Data path
• Computational PE
• Conditional PE
• Runtime
• Enable / Disable PEs and modules
• Data format

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General Model of the Processing Element
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Simulink PE model (Data path)
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Simulink PE model (Data path)

• Unconditional PE
• Delay
• Shift right or left
• (X Y)
• (X Y)
• (X Y) Z
• (X - Y) Z
• (XY Z)
• (XY Z)
• C0, C1

• Conditional PE
• If (condition) then
• Perform task A
• Else
• Perform task B

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Simulink PE model (Run Time)

• Fire pattern
• Example
• Fire pattern 1 PE always enable
• Fire pattern 1 0 PE enable every other
  instruction
• Fire pattern 1 0 0 0 PE enable every 4th
  instruction
• Potential applications
• Multi-rate Signal Processing
• Multi-functionality in one FPPA

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FFPA graphical interface design flow
Note SIFOpt tool is a result of David M.
Buehler dissertation at the University of Idaho.
Algorithm
Simulink

• Model (floating point)
• Design Data Path
• Provide Input data
• Data format
• Run time

Validation
result
Golden model
result
PERL (floating ? fixed point)
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Example 1 Realizing 4 tap FIR filter
Difference Equation
Input waveform
Output waveform
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Example 2 Wavelet (Multi-rate filter bank)
Source
L1
L2
L3
L4

• Low Pass filter
• 4 taps with Debenchies coefficients
• Debenchies coefficients are normalized by
  sqrt(2) to get the sum equal to one

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Example 2 Model 4 series filters
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Example 2 Model Down Sampling
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Example 2 FPPA view
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Example 2 Simulation result
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Future work

• Data path optimization
• Speed
• Area
• Cook book for common use circuits
• Square root
• Division
• Trigonometry functions
• Iterative methods
• Down / Up sample
• Matrix computation

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Summary

• Present FPPA
• FPPA programming complexity
• Graphical programming environment
• Intuitive
• Fast and easy
• Validation and Verification
• Matlab gt Floating point
• FPPAsim gt hardware specific
• Compile to FPPA code

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