Cache memory Homework

1
Cache memory Homework Q1

• A computer has a 32 bit address and a 64 bit data
  bus with address resolution to the byte level.
  The computer is using a direct mapped cache with
  4K cache lines. The size of each cache line is 64
  bytes.
• What is the size of the cache?
• How many bits are there in the line, the index
  and the tag fields?  
• What is the size of the tag memory?
• How many memory cycles are required to fill up a
  cache line?

Solution
32-bit address bus
Tag
Index
Line
64 bytes per line
Data
Tag
4K Cache lines
2
Cache memory Homework Q1

• What is the size of the cache?
• Cache size 4K lines X 64 bytes/line 4K X 64
  256Kbytes
• How many bits are there in the line, the index
  and the tag fields?
•   Line bits 2L 64 26 ? Number of line bits
  6
•   Index bits 2N 4K 22 X 210 212 ? Number
  of index bits 12
• Number of tag bits Size of address bus -
  Number of line bits - Number of index bits
• 32 6 12 14 bits
• What is the size of the tag memory?
• Size of tag memory Number of cache lines X
  Number of tag bits
• 4K x 14 bits
• How many memory cycles are required to fill up a
  cache line?
• Number of memory cycles Size of cache line /
  Size of data bus (in bytes)
• 64 / (64/8) 64 / 8 8 cycles

3
Cache memory Homework Q2

• A computer has a 32-bit address bus with a direct
  mapped cache, using 4 line bits, 16 tag bits and
  12 index bits.
• Specify
• The cache block size
• The size of the cache
• The size of the tag memory
• Specify whether the following address pairs can
  be placed in the cache simultaneously.
• i. 3AC6F456 and 26A35456
• ii. 3F08C304 and 3F08C371
• iii. 5E3C7680 and 8F3C768A
• iv. 22334455 and 2233445C

Data
Tag
Solution
32-bit address bus
Tag
Index
Line
12 bits
4 bits
4
Cache memory Homework Q2

• a.i) Number of blocks 2(number of index bits)
  212 22 x 210 4K
• Size of the cache Number of blocks x Block
  size 4K x 16 64Kbytes
• a.ii) Block size 2(number of line bits) 24
  16 bytes
• a.iii) Size of the tag memory Number of blocks
  x Number of tag bits
• 4K x 16 bits
• Specify whether the following address pairs can
  be placed in the cache simultaneously.

Address Address Address Answer Yes/No Justification
Tag Index Line Answer Yes/No Justification
i 3AC6 F45 6 Yes Different index
i 26A3 545 6 Yes Different index
ii 3F08 C30 4 Yes Different index
ii 3F08 C37 1 Yes Different index
iii 5E3C 768 0 No Same index and different tag
iii 8F3C 768 A No Same index and different tag
iv 2233 445 5 Yes Same index and same tag, i.e same cache block
iv 2233 445 C Yes Same index and same tag, i.e same cache block