68230 Parallel Interface/Timer

1
68230 Parallel Interface/Timer

• Outline
• I/O Fundamentals
• PI/T Structure
• PI/T Operating Modes
• PI/T Registers
• PI/T Timer Functions
• PI/T Application Example
• Goal
• Understand 68230 functions and usage
• Understand 68230 programming
• Reading
• Microprocessor Systems Design, Clements, Ch. 8.3

2
I/O Fundamentals

• Basic I/O port functions
• handshaking
• data transfers interlocked so previous transfer
  complete before next can start
• buffering
• permits overlap of data transfer between CPU and
  PI/T and between PI/T and peripheral
• requires storage within PI/T

3
Input Handshaking

• Similar to 68000 memory read
• PI/T Signals
• H1 - edge sensitive input
• H1S signal set by input transition
• H2 - output
• parallel I/O bus PA0-7
• Example
• single-buffered input
• H2 - PI/T received data signal to peripheral
• H1 - data ready signal from peripheral

4
Input Handshaking (cont.)

• Double buffering
• initial input latches
• final input latches
• Data can come from peripheral until both latches
  full
• do not assert H2 until initial latch is empty
• CPU reads data from final latch while initial
  latch being filled
• hides latency of device driver
• CPU looks at H1S bit to see if PI/T has data to
  read

5
Output Handshaking

• Similar to 68000 memory write
• Similar to input handshaking
• H2 - data ready signal from PI/T
• H1 - received data signal from peripheral
• Double buffering
• initial and final output buffers
• data can be sent to peripheral until both latches
  empty
• overlap CPU write and write to peripheral
• CPU looks at H1S bit to know when PI/T has empty
  buffer

6
PI/T Structure

• Asynchronous memory bus interface
• 8-bit data I/O
• vectored interrupts
• A and B 8-bit programmable I/O ports
• PA0-7 and PB0-7 - data pins
• H1/H2 and H3/H4 - handshaking signals
• C dual-function port
• unbuffered, no handshaking 8-bit I/O port PC0-7
• 24-bit timer w/5-bit prescaler
• counts clock or Tin/PC2 pulses
• single or periodic pulses on Tout/PC3 or use as
  IRQ
• TIACK/PC7 - IACK for Tout request
• interrupt interface
• PIRQ/PC5 - IRQ for A and B
• PIACK/PC6 - IACK
• support for DMA controller
• DMAREQ/PC4 - DMA request output for A and B

7
68230 Registers

• 23 internal registers
• selected via register select pins RS1-5
• registers 23-31 are null registers returning 00
• Functions
• control and status registers
• port A and B data and direction registers
• counter/timer registers

8
PI/T Operating Modes

• A and B ports have 7 operating modes
• 4 modes plus submodes
• Modes control buffering, port pairing
• Both ports must operate in same mode
• can have independent submodes
• Mode 0
• bits 6 and 7 of PGCR 0
• bits 7 and 6 of PACR or PBCR set 00, 01, 1X
  submodes
• PADDR and PBDDR data direction register for A and
  B
• each bit determines direction of port pin
• 0 - input pin, 1 - output pin
• zeroed on reset
• unidirectional mode since pin directions fixed by
  DDRs
• submodes determine input and output buffering
• double-buffered data direction is primary
  direction of port
• handshaking with H1/H2 for A, H3/H4 for B

9
Operaing Modes (cont.)

• Mode 0, Submode 00
• double-buffered input in primary direction
• single-buffered output from PI/T
• latch input on rising H1
• H2 controlled by PACR3-5
• output
• interlocked handshake
• pulsed handshake - negate automatically after 4
  clock cycles
• H1S and H2S status bits at PSR0-1
• Mode 0, Submode 01
• primary direction from PI/T, double-buffered
  output
• input is nonlatched - CPU gets whatever is there
• PACR00 - H1S set if either output latch can
  accept data
• PACR01 - H1S set if both latches are empty

10
Operating Modes (cont.)

• Mode 0, Submode 1X
• bidirectional I/O
• no double-buffering
• inputs are nonlatched
• outputs are single-buffered
• H1 edge sensitive input only, does no handshaking
• H2 can be edge-sensitive input setting H2S
• H2 can be output
• Mode 1
• A and B combined into 1 16-bit port
• double-buffering in primary direction and
  handshake control
• H3/H4 used for handshake
• PBCR provides control
• can use PACR with H1/H2 for extra functions
• H1 - edge-sensitive input
• H2 edge-sensitive input or output

11
Operating Modes (cont.)

• Mode 1, Submode X0
• double-buffered inputs or single-buffered outputs
• 16-bit words transferred as 2 bytes to/from CPU
• read A before B
• A has most significant byte
• data latched on H3
• H4 can be output, input, or handshake
• output pins have single latch
• Mode 1, Submode X1
• double-buffered outputs or nonlatched inputs
• write A before B, then PI/T transfers data to
  output
• port A control and H1/H2 similar to mode 1,
  submode X0
• port B control and H3/H4 similar
• PBCR00, H3S set when either buffer can accept
  data
• PBCR01, H3S set when both ports are empty

12
Operating Modes (cont.)

• Mode 2
• bidirectional I/O
• A - no handshaking, unlatched input,
  single-buffered output
• DDR sets primary data direction of each pin
• B - bidirectional, 8-bit, double-buffered port
• all pins in same direction
• H1/H2 control output handshaking
• H3/H4 control input handshaking
• H1 determines port direction - peripheral sets
  direction
• H1 negated, port is output
• Mode 3
• 16-bit double-buffered bidirectional I/O
• similar operation to mode 2

13
PI/T Registers

• Port General Control Register (PGCR, offset 00)
• operating mode and H1-H4 control for PI/T
• Port Service Request Register (PSRR, offset 02)
• when to generate interrupt or DMA request
• Port Data Direction Registers (PDDRA, offset 04,
  PDDRB, offset 06, PDDRC, offset 08)
• set bits to 1 for output, 0 for input, zeroed on
  reset
• Port Interrupt Vector Register (PIVR, offset 0A)
• upper 6 bits of 4 port interrupt vectors
• 2 LSBs specify source as H1-H4
• initialized to 0F (uninitialized vector) after
  reset
• Port Control Registers (PCRA, offset 0C, PCRB,
  offset 0E)
• port submodes and handskaing

14
PI/T Registers (cont.)

• Port Data Registers (PADR, offset 10, PBDR,
  offset 12, PCDR, offset 18)
• A and B are holding registers for CPU-side bus
• PCDR function depends on R/W and C function
• contents not changed by PI/T reset
• Port Alternate Registers (PAAR, offset 14, PBAR,
  offset 16)
• read-only instantaneous state of port pins
• write generates DTACK, but no effect
• Port Status Register (PSR, offset 1A)
• handshake pin status bits, instant handshake pin
  values

15
PI/T Timer Functions

• Timer
• 24-bit counter
• load with 3 bytes - high, middle, low
• TSR (timer status register) and TCR (timer
  control register)
• load with value, count to zero - ZDS (zero detect
  status) bit set
• select clock rate to count - can prescale
  (divide) by 32
• assert Tout at zero, can use to generate IRQ
• have TIVR interrupt vector
• clock with CLK or Tin
• can automatically reload at zero or roll over
• from preload register
• Timer in halt or run state

16
PI/T Timer Applications

• Real-time clock
• generate interrupts at periodic interval
• use for OS context switching
• reload counter on zero
• Tout used to interrupt CPU
• CPU must zero ZDS bit to remove interrupt
• Square-wave generator
• square wave at Tout pin
• TCR70, Tout toggled whenever counter is zero
• Interrupt after time-out
• counter rolls over after zero
• allows CPU to see how long to service interrupt
• Elapsed time measurement
• CPU starts timer with FFFFF in preload register
• CPU stops timer, reads value
• can also use to count pulses on Tin
• can also set Tin to enable counter when high

17
PI/T Application - Centronics Interface

• Centronics printer interface specification
• 8-bit data
• control signals and timing
• Handshaking signals
• DSTB (data strobe) - tell printer data is
  present
• ACKNLG (acknowledge) - tell interface data is
  taken
• Printer status signals
• BUSY - printer is busy, will only accept DC 1
  input
• asserted in response to DSTB
• SLCT (select) - printer is online
• PE (printer error) - out of paper
• Unused signals
• INPRM - printer stops and initializes
• FAULT - out of paper or off-line
• AUTO LINE FEED - automatic carriage return at
  EOL
• SLCT-IN - printer in select mode (online)

18
Centronics Device Driver

• Example
• transmit ASCII characters (7-bits) to line
  printer
• interrupt-driven character transmission
• Driver subroutines
• LPOPEN - initialize printer port
• LPWRITE - put characters in buffer, check printer
  status
• LPINTR - interrupt service routine, send
  characters to printer

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Driver Memory Locations

• PI/T definitions
• PIT EQU 0C0000 Base address of PI/T
• PGCR EQU PIT1 Port general control reg
• PSRR EQU PIT3 Port service request reg
• PADDR EQU PIT5 Port A data direction reg
• PIVR EQU PITB Port interrupt vector reg
• PACR EQU PITD Port A control reg
• PADR EQU PIT11 Port A data register
• PCDR EQU PIT19 Port C data register
• PSR EQU PIT1B Port status register
• BUFADDR DS.L 1 Memory for buffer pointer
• BYTECNT DS.L 1 Memory for byte counter
• FINFLAG DS.B 1 Memory for finish flag

20
LPOPEN Subroutine

• Functions
• set port A to 7-bit, double-buffered
  unidirectional output
• PA7 set to unbuffered input
• program H2 to provide 4-cycle pulse output
  handshake
• FINFLAG set to FF when printer finished,
  otherwise 00
• LPOPEN MOVE.B FF,FINFLAG FINFLAGFF when
  printer
• finished and idle
• MOVE.B 7F,PADDR port A 7-bit output
• 1-bit input
• MOVE.B 78,PACR port A submode 01
• pulsed H2
• MOVE.B 10,PGCR enable port A, mode 0
• MOVE.B 40,PIVR load PIT interrupt vector
• with 40 (handler at 100)
• MOVE.B 18,PSRR enable PIT interrupt pins
• RTS

21
LPWRITE Subroutine

• Function
• called by user via TRAP instruction
• byte count in D0, A0 points to data buffer
• if printer online, enable interrupts, put status
  in D0 on exit
• LPWRITE CLR.B FINFLAG Reset finished flag
• MOVE.L D0,BYTECNT Save byte cnt
• MOVE.L A0,BUFADDR Save buf ptr
• BTST 0,PCDR Test PrinterError
• status on pin PC0
• BEQ.S PError If 0, then error
• BTST 1,PCDR Test SLCT status on
• pin PC1 (PrinterOnLine)
• BEQ.S LPWG0 If 0, printer online
• PError MOVE.B FF,D0 Set D0FF (error)
• RTS
• LPWG0 BSET 1,PACR Enable H1S interrupt
• LPW1 TST.B FINFLAG Wait until FINFLAGFF
• BEQ.S LPW1 FINFLAG set by LPINTR

22
LPINTR Subroutine

• Function
• handle printer interrupt
• get characters from printer buffer and send to
  PI/T
• disable interrupts when printing complete
• LPINTR MOVE.L A0,-(SP) Save current A0
• MOVEA.L BUFADDR,A0 Get buf ptr
• TST.L BYTECNT Check char cnt
• BEQ.S EMPTY if 0, then done
• PRINT MOVE.B (A0),PADR send char to PI/T
• SUBQ.L 1,BYTECNT decr char counter
• BEQ.S EMPTY if 0, then done
• BTST 0,PSR Room in PI/T for a char?
• BNE PRINT if room, send char, else
• BRA NOTRDY PI/T full, not ready
• EMPTY BCLR 1,PACR Disable H1S interrupts
• MOVE.B FF,FINFLAG FINFLAGFF, finished
• NOTRDY MOVE.L A0,BUFADDR Save buf ptr
• MOVE.L (SP),A0 Restore original A0