CAD Issues

1
CAD Issues Algorithms(1)
2
CAD Issues Algorithms

• 1. Simulation
• 2. Verification
• 3. Synthesis
• 4. Place Route

3
1. Simulation 1) Circuit Simulation

• Function
• DC analysis, AC analysis, noise analysis,
  transient or time-domain analysis
• very accurate but spends much time
• Method
• treat the circuit as a continuous dynamical
  system and obtain a set of nonlinear
  algebraic-differential equations with electrical
  variables such as voltage, current, and charge to
  describe its behavior
• Gaussian elimination O(N3), Nnumber of nodes
• Sparse matrix O(N1.5), only neighboring nodes
  have interconnecting elements to reduce analysis
  time
• SPICE
• the very popular circuit simulation tool
  developed at Berkeley
• HSPICE - most commercially used

4
Circuit simulation algorithm
Nonlinear differential equation f(x,x,t) 0
Nonlinear simultaneous equations g(x) 0
Linear simultaneous equations Ax b
5
2) Switch-level Simulation

• Motivation
• SPICE simulation is too slow for a large digital
  system.
• Logic simulation may give misleading simulation
  results for systems built from MOS transistors lt-
  bidirectionality of signal flow, charge sharing
  effects, and transistor sizes.
• Switch-level simulation is the lowest level of
  digital simulation.

transistor as a gate-controlled switch
6
Network model
Storage node state is determined by the
operation of network
Vdd
Input node strong signals to the system, ex)
Vdd, Gnd, clock, data inputs
out
(4,1)
2
3
gnd
(4,0)
(s) Edge transistor s strength, or
conductance relative to those of TRs in a ratioed
circuit
(c, l) c node capacitance relative to that of
other nodes with which it may share charge, Vdd,
Gnd has maximum value l logic level, one of (0,
1, X)
Range of c and s 1ltcltK, for storage
nodes KltsltW, for transistor strength c W,
for input nodes
7
Network partitioning
Gate input is terminated
Each subnetwork is simulated to find steady-state
response
8
Steady-state response of subnetwork
Strength of conducting path min(size(root(p)),
min(strength of transistors))
Strength and level of storage node
9
3) Logic Simulation

• Simulation model
• using logic gate model - AND, OR, NOT, NAND, NOR,
  Flip-Flop, etc.
• I/O value representation - Boolean logic value
  0, 1, X(unknown)
• time - integer, defined by a multiple of unit
  delay
• Classification by delay consideration
• unit-delay simulator
• assumes that each component has a unit delay
• avoids modeling any circuit delays
• iii) simulates function but not performance
• variable-delay simulator
• i) allow components to have arbitrary delays
• ii) allow for more accurate modeling of
  fast-changing nets

10

• Delay model
• model delays physically occurring in logic gates
• enable accurate performance analysis of the
  logic designed
• embedded in logic simulation engines
• transport delay, ambiguity delay, rise-fall
  delay, inertial delay

A
B
?I1, ?T1
Transport delay
B
?I4
Inertial delay minimum duration for changing gate
state
11

• Event-driven simulation
• evaluate a component only when an even occurs on
  its input
• keep track of event on a time wheel, which stores
  event in time order
• spin the time wheel forward to the next time slot
  with an event, and start simulating from there
• evaluating a component can cause a new event to
  be added to later slots in the time wheel for
  later action

Delay X,W1 Y,Z2
12

• Compiled simulation
• translate the given logic circuit into a fast
  code which is compiled and executed
• 1. Do a levelization - determining evaluation
  order of gates in the given circuit for correct
  simulation, a kind of topological sorting
• 2. Generate code for evaluating each gate from
  lower level to high level
• 3. Compile the generated code
• 4. Run the compiled code

/ level 1 / fbc store P, f gde store
Q,g / level 2 / haf store
R,h ifg store S,i / level 3
/ jhi store T, j
13
4) Fault Simulation

• Digital logic testing
• defect physical deviation from some specified
  properties
• error incorrect response to applied stimuli
  caused by the presence of defects
• test an experiment to detect defects and the
  source of them
• Fault model
• models defects introduced during manufacturing
• stuck-at-0(/1) the defect causes a logic gate
  output to be always 0(or 1)
• Single fault assumption only one fault at any
  time in a circuit

This input pattern can detect the fault
1 --gt
1 --gt
--gt 1
--gt 0
1 --gt
1 --gt
Fault-free circuit
Bottom input is s-a-0
14
start
Initial fault list
Fault coverage
Generate stimulus to cover some remaining faults
100
Fault simulation
Remove faults covered from fault list
of test vectors
Coverage OK?
stop
Test pattern generation satisfying target coverage
15

• Appications
• evaluation of a test sequence in terms of its
  fault detection and location capability
• analysis of circuit under failure condition
• Methods
• general
• i) serial
• ii) parallel
• iii) deductive
• iv) concurrent
• combinational circuits
• i) parallel pattern methods
• ii) trace-based
• iii) combined
• synchronous sequential circuits
• i) modified parallel(PROOFS)

Fault simulation
16

• Serial fault simulation
• iteration of logic simulation after injecting
  each fault -gt heavy simulation time
• Parallel fault simulation
• simulating fault-free circuit and N-1 faulty
  circuits simultaneously
• N word size of host machine

A,B,C 4 bit value C A B performs 4
evaluations in parallel
17

• Deductive fault simulation
• simulate a large of faults in one pass
• only a few faults may produce values different
  from fault-free values
• approach - keep fault-free values and differences

Fault list a set of faults that complement the
fault-free value at a line
After simulation of fault-free circuit, fault
list is deductively constructed based on the
fault-free logic values on each line
This can detect a/1 --gt Laa/1
This can i)detect c/1 ii)La because a has
controlling value and Lb is eliminated because b
has non-controlling value ? Lc(La - Lb) U c/1
This can detect b/0 --gt Lbb/0
18
La a/1 Lb b/0 Ld d/1 Le (La -
Lb) U e/0 a/1, e/0, Lf (Ld - Lb) U f/1
d/1, f/1 Lg (Le - Lf) U g/0 a/1, e/0,
g/0 ----gt input pattern 010 can detect faults
a/1,e/0 and g/0
19

• Concurrent fault simulation
• keep a fault list(with I/O values) for each gate
• when inputs to a gate change or faults are
  propagated, dynamically update the fault list for
  the gate

Input pattern abdf0000 detect faults f/1 and g/0
Input pattern abdf1001 detect faults
b/1,c/0,e/0,f/0, and g/1
20
Comparison of three methods
21
2. Verification 1) Timing Verification

• ??? ??? ??? ??? ??? ?? ??? ? ?? ?? ???? ?? ???
  ???? ???? ?? ??? ?? ??.
• Critical delay (TC)? critical path
• Primary output? ?? ??? ??? ??? ??? ?? ? ??? ??
  ??.
• TC? ?? ??(TCLK) ?? ?? ??? ??? ?? ????.

TC lt TCLK
22

• Topologically longest path
• ??? ??? ?? ? ??.
• ??? ?? ???? ??? ??? ?? ? ?? (false path problem).

0
0
10
10
20
20
1
1
Topologically longest path 40 Actual delay 30
23

• ??? ????? (Dynamic timing analysis)
• ??? ?? ??? ???? ????? ?? ???? ???? ??? ???.
• ?? ???? ??? ???? ??? ? ??.
• ????? ??? ?? ??? ?? ????? ???? ????? ??? ???? ??
  ??????? ????.

24

• Static Timing analysis
• Best first search? ??? ?? ??.
• i) Topologically longest path? false path? ????
  ????.
• ii) ??? sensitizable path?? critical path? ??.
• iii) False path? ?? ???? ? ??? ??? ?? ??? ????.
• False path??? ????? ??? ???? ??? path
  sensitization criteria? ???? ????.
• i) Path sensitization criteria? ??? ??? ???? ???
  ?? ???? ??? ???? ??? ??? ???? ???? ?? ???? ??
  ???? ??? ?? Timing analysis? ???? ????.
• ii) ????? ???? ???? ??? ??? ? ?? path
  sensitization criteria? ???? ??.

25
2) Functional Verification

• ??
• ??? ??? system? ??? functional spec.? ????? ????
  ??
• Complete verification ??
• Implicit enumeration method
• BDD-based method
• Formal method
• Equivalence checking, correctness checking

Specification
Golden Reference Model (Ideal model)
Design
Equivalence
Correctness
26

• Implicit Enumeration-State machine
• ??
• i) ??? ??? state machine?? ?? input sequence? ??
  ?? output sequence? ?? state pair? ???.
• ??
• i) State machine S, Q ? si? S? state, qi? Q?
  state
• ii) si? qi? ?? ??? ?? ??? ??? ????, ?? ??? ??? ??
  ??? ?? next state? ?????? ???? ????.

s0 ? q0
i2
i3/o3
i1
s2 ? q1
s1 ? q0
i2/o2
i3/o3
i1/o1
i1
i2
i1/o1
i1/o1
s0 ? q0
s2 ? q1
i2/o2
i2/o2
i3
s0 ? q0
27

• BDD(Binary Decision Diagram)
• ??
• i) Internal node Variable? ???
• ii) Leaf node 0, 1 ? ??? ??? function? ?? ???
• iii) Edge Variable? 0 ? ?, 1 ? ?? ??? ???
• iv) 0 edge? 1 edge? ?? internal node? ???.
• ??
• i) Variable ??? ??? functionality? ?? ??? ???
  ???.
• ii) BDD ???? operation? ??? ?? recursive
  equation?? ????.

28
x1

• BDD ??
• Combinational network? equivalence check
• ? network? ?? ?? variable ??? BDD? ??? reduction
  ??. (ROBDD)
• ? BDD? isomorphic ?? equivalent ??.

1
0
x2
0
F x1x2 x3
x3
1
1
0
0
1
29

• Formal verification
• Design? specification? ?? ??? ??? ??? ??? ?
  language? ??? ??, symbolic manipulation? ????
  ???? ??
• Higher-order logic ?? temporal logic ??? spec?
  design? ???? theorem prover? ??, logic? ???? ???
  ?? ???.
• Temporal logic
• ??? predicate logic? ???? ??? ???? ??? ??
• Finite state system? state transition graph?
  ??????, ?? temporal logic?? formulation? ????.

30

• Computational Tree Logic (CTL)
• State transition graph? ?? initial state? root? ?
  infinite tree? ???. ? tree? path? system? ?? ???
  state? ? state? ???? ??? ????.

31

• CTL? ??
• Path quantifier (A, E)
• i) A ?? ??? ??? (?? ?? ??? state )
• ii) E ?? ??? ??? (?? ?? ??? state )
• Temporal modality(F, G, X, U)
• i) F ? ? ? ?? state?? ??? ?? ?? ???.
• ii) G ? ? ? ?? state?? ?? ??? ???.
• iii) X ? ? ? ?? state? ?? ?? state?? ??? ???.
• iv) ? U ? ? ? ?? state ?? ??? ?? ??, ? ??
  state?? ? ? ?? ??? ???.

32

• Traffic light controller specification
• hwy_light ? farm_light? ??? green? ??? ???.
• i) farm_light? hwy_light? ??? green? ??? ?? ???,
  ?? ????? ??.
• ii) AG ( !((farm_light green)
  (hwy_lightgreen)))
• farm road? ?? ???? ?? hwy_light? ??? green? ???
  ??.
• i) ?? ??? ?? ??? hwy_light? green? ?? ??? ?? ???
  ?? ?? ???? ??.
• ii) AG(AF(hwy_lightgreen))