Assembly Language

1
Assembly Language

• Chapter 3

2
Computer Languages

• High-level languages
• Java, Python, C, ASP, HTML,
• Low-level languages
• Assembly language symbolic representation of
  machine instructions.
• Assembler a compiler which translates from an
  assembly language to a machine language.
• Machine languages

3
Components of a computer More detail
processor
memory
registers
ALU
data
program
Instruction register
Program counter
data
address
Control units
4
Levels of descriptions of computer systems

• computer architecture begins at the instruction
  set.
• An instruction set is what a programmer at the
  lowest level sees of a processor
• one instruction set with different level of
  performance for many models, based on the
  implementation of a control unit via
  microprogram.
• Present day processor designs converge, their
  instruction sets become more similar than
  different.

5
Registers

• Name Reg. No. Usage
• zero 0 hardwired 0
• v0-v1 2-3 return value and expression
  evaluation
• a0-a3 4-7 arguments
• t0-t7 8-15 temporary values
• s0-s7 16-23 saved values
• t8-t9 24-25 more temporary values
• gp 28 global pointer
• sp 29 stack pointer
• fp 30 frame pointer
• ra 31 return address

6
MIPS operands
Name Example Comments
32 registers 0, 1, 2,..., 31 Fast location for data. In MIPS, data must be in registers to perform arithmetic.
memory words Memory0, Memory4,..., Memory4293967292 Accessed only by data transfer instructions. MIPS uses byte addresses, so sequential words differ by 4. Memory holds data structures, such as arrays, and spilled registers, such as those saved on procedure calls
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MIPS Assembly Instructions Arithmetic
Instruction Example Meaning Comments
add add rd,rs,rt rd rs rt 3 operands data in registers
subtract sub rd,rs,rt rd rs - rt 3 operands data in registers
add unsigned addu rd,rs,rt rd rs rt 3 operands data in registers
subtract unsigned subu rd,rs,rt rd rs - rt 3 operands data in registers
add immediate addi rd,rs, 100 rd rs 100 3 operands data in registers and a constant
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MIPS Assembly Instructions Data Transfer
Instruction Example Meaning Comments
load word lw rt, 10(rs) rt Memoryrs10 Data from memory to register
store word sw rt, 10(rs) Memoryrs10 rt Data from register to memory
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MIPS Assembly Instructions Logical
Instruction Example Meaning Comments
and and rd,rs,rt rd rd rt 3 register operands bitwise operation
or or rd,rs,rt rd rd rt 3 register operands bitwise operation
nor nor rd,rs,rt rd (rd rt) 3 register operands bitwise operation
and immediate andi rt,rs,10 rt rs 10 bitwise operation with constant
or immediate ori rt,rs,10 rt rs 10 bitwise operation with constant
shift left logical sll rd,rt,10 rd rt ltlt 10 Shift left/right by constant
shift right logical srl rd,rt,10 rd rt gtgt 10 Shift left/right by constant
10
MIPS Assembly Instructions
Instruction Example Meaning Comments
jump j 10000 goto 10000 Jump to target addr.
jump register j 31 goto 31 For switch, procedure return
jump and link jal 1000 31 PC4 go to 1000 For procedure call
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MIPS Assembly Instructions Conditionals
Instruction Example Meaning Comments
branch on beq rs,rt,100 if (rs rt) go to PC4100 Equal test PC relative branch
branch on not bne rs,rt,100 if (rs ! rt) go to PC4100 Not equal test PC relative branch
set on lt slt rd,rs,rt if (rs lt rt) rd 1 else rd 0 Compare lt 2s complement
set lt immediate slti rt,rs,100 if (rs lt 100) rt 1 else rt 0 Compare lt constant 2s complement
set lt unsigned sltu rd,rs,rt if (rs lt rt) rd 1 else rd 0 Compare lt natural number
set lt immediate unsigned sltiu rt,rs,100 (rs lt 100) rt 1 else rt 0 Compare lt constant natural number
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Example

• x yz5
• w z-y
• lw t0, 18(zero) load y
• lw t1, 22(zero) load z
• add t2, t0, t1 yz
• addi t2, t2, 5 (yz)5
• sw t2, 14(zero) store x
• sub t3, t1, t2 z-y
• sw t3, 10(zero) store w

• if (altb) a
• else b
• lw t0, 50(zero) load a
• lw t1, 54(zero) load b
• slt t2, t0, t1 altb
• beq t2, zero, else if
• addi t0, t0, 1 a
• sw t0, 50(zero) store a
• else
• addi t1, t1, 1 b
• sw t1, 54(zero) store b

10 14 18 22
50 54
w x y z
a b
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Basic instruction formats
R- format
31 26 25 21 20 16 15 11 10 6 5 0
op rs rt rd Shamt funct
I- format
31 26 25 21 20 16 15 0
Op rs rt Const/addr
J- format
31 26 25 0
Op code address
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Instruction Representation Examples
Instruction Format Op rs rt rd Shamt funct Const/addr
add rs,rt,rd R 00 reg reg reg 00 20 NA
sub rs,rt,rd R 00 reg reg reg 00 22 NA
addi rs,rt, 100 I 08 reg reg NA NA NA const
j 10000 J 02 NA NA NA NA NA addr
beq rs,rt, 1000 I 04 reg reg NA NA NA const
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Instruction Representation Examples
Instruction Format Op rs rt rd Shamt funct Const/addr
add rs,rt,rd R 00 reg reg reg 00 20 NA
add t0, t1, t2
31 26 25 21 20 16 15 11 10 6 5 0
op rs rt rd Shamt funct
0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0
0 1 0 9 5 0 3 0
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Instruction Representation Examples
Instruction Format Op rs rt rd Shamt funct Const/addr
sub rs,rt,rd R 00 reg reg reg 00 22 NA
sub s0, s1, s2
31 26 25 21 20 16 15 11 10 6 5 0
op rs rt rd Shamt funct
0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0
0 2 1 1 9 0 2 2
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Instruction Representation Examples
Instruction Format Op rs rt rd Shamt funct Const/addr
addi rs,rt, 100 I 08 reg reg NA NA NA const
addi s0, s1, 100
31 26 25 21 20 16 15 0
op rs rt Const/addr
0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 1 0 1 1 0 0
2 2 1 1 0 C A C
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Instruction Representation Examples
Instruction Format Op rs rt rd Shamt funct Const/addr
j 10000 J 02 NA NA NA NA NA addr
j 10000
31 26 25 0
op Const/addr
0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 0 0 0 1 0 0 0 0
0 8 0 0 2 7 1 0
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Instruction Representation Examples
Instruction Format Op rs rt rd Shamt funct Const/addr
beq rs,rt, 1000 I 04 reg reg NA NA NA const
beq s0, s1, 100
31 26 25 21 20 16 15 0
op rs rt Const/addr
0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 1 0 1 1 0 0
1 2 1 1 0 C A C
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MIPS Simulator

• http//pages.cs.wisc.edu/larus/spim.html

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Case/ Switch statement

• switch (i)
• case 0 i break
• case 1 j break
• case 4 k
• Jump (address) table
• Table storing addresses of different cases

3010 2010 k0
3014 2045 k1
3018 2077 k2
301C 2077 k3
3020 2085 k4
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Case statement and jr instruction

• switch (i)
• case 0
• i
• break
• case 1
• j
• break
• case 4
• k

• variable i is in t1, const 5 is in t0
• start addr of jump table (e.g. 3010) is in s0
• blt t1, zero, out
• bge t1, t0, out
• multiply i by 4 for word size
• sll t1, t1, 2
• find entry in the jump table
• add t1, t1, s0
• load addr in jump table to t2
• lw t2, 0(t1)
• jr t2
• L2010
• j out
• L20485

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Procedure calls

• Steps to Execute procedure
• place parameters in a place where procedure can
  access them
• transfer control to the procedure
• acquire the storage needed for the procedure
• perform the desired task
• place the result value in a place where the
  calling program can access it
• return to the control point of origin

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Memory allocation for programs
sp
Stack Heap (dynamic data) Static
data Code (text segment) Reserved
fp
gp
pc
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Registers

• a0-a3
• four argument registers in which to pass
  parameters
• v0-v1
• two value registers in which to return values
• ra
• one return address register to return to the
  point of origin

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jal jump and link

• jumps to an address and simultaneously saves the
  address of the following instruction in register
  ra
• jal ProcedureAddress
• jal puts PC 4 in ra
• to return, after completion of the procedure
• jr ra
• calling program (caller) puts parameter values in
  a0-a3
• callee performs calculations and places result in
  v0-v1

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Call sequence

• Put arguments in a0-a3
• The rest of the arguments (if exist) are placed
  in the frame or activation record
• Allocate a frame in stack (update sp)
• Save values of s0-s7, fp, ra in the frame
• Update fp
• Execute jal instruction

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Return sequence

• Put the return value in v0
• Restore registers s0-s7
• Restore fp
• Pop the frame from stack
• Execute jr ra

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Example 1

• int leaf_example (int g, int h, int i, int j)
• int f
• f (g h) - (i j) return f
• leaf example
• addi sp, sp, -12 adjust stack to make room
  for 3 items
• sw t1, 8(sp) save register t1 for use
  afterwards
• sw t0, 4(sp) save register t0 for use
  afterwards
• sw s0, 0(sp) save register s0 for use
  afterwards
• add t0, a0, a1 register t0 contains g h
• add t1, a2, a3 register t1 contains i j
• sub s0, t0, t1 f t0 - t1, which is
  (gh)-(ij)
• add v0, s0, zero returns f (v0 s0 0)
• lw s0, 0(sp) restore register s0 for caller
• lw t0, 4(sp) restore register t0 for caller
• lw t1, 8(sp) restore register t1 for caller
• addi sp, sp, 12 adjust stack to delete 3
  items
• jr ra jump back to calling routing

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Example 2

• int fact (int n)
• if (nlt2) return(1) else return(nfact(n-1)
• fact
• addi sp, sp, -8 adjust stack to make room for
  2 items
• sw ra, 4(sp) save the return address
• sw a0, 0(sp) save the argument n
• slti t0, a0, 2 test for nlt2
• beq t0, zero, L1 if ngt2 goto L1
• addi sp, sp, 8 adjust stack to delete 2 items
• addi v0, zero, 1 else return 1
• jr ra jump back to calling routing
• L1
• addi a0, a0, -1 if ngt1 calculate n-1
• jal fact call fact with n-1
• lw a0, 0(sp) return from jal, restore
  argument
• lw ra, 4(sp) restore return address
• addi sp, sp, 8 adjust stack to delete 2 items
• mul v0, a0, v0 return n fact(n-1)

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Execution example
int fact (int n) if (nlt2) return(1) else
return(nfact(n-1) fact(2)

• fact
• addi sp, sp, -8
• sw ra, 4(sp)
• sw a0, 0(sp)
• slti t0, a0, 2
• beq t0, zero, L1
• addi sp, sp, 8
• addi v0, zero, 1
• jr ra
• L1
• addi a0, a0, -1
• jal fact
• lw a0, 0(sp)
• lw ra, 4(sp)
• addi sp, sp, 8
• mul v0, a0, v0
• jr ra

Push frame
Call fact (2) addi a0, zero, 2 (03A0)
jal fact
a0 2
nlt2 ret 1
1
stack
03A4 (ra) 2(a0)
ra 03A4
0344
(0340)
0344 (ra) 1(a0)
restore
v0 1
2
ngt2 ret n(n-1)!
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32-bit constants

• A register can contain an integer between
  -2147483648 (-231) and 2147483647
• Immediate data can be between -32768 (-215) and
  32767
• addi t0, zero, 32767
• How can we use 32-bit constant?
• lui (load upper immediate) instruction

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load upper immediate instruction lui

• Store 16-bit immediate data in the upper half of
  the register
• lui t0, 16384 put 0100 0000 0000 0000 in the
  upper half of t0
• To store a 32-bit constant in a register
• add t0, zero, zero
• lui t0, 16384
• addi t0, t0, 5435

0100 0000 0000 0000
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Jumping to far-away instruction

• In beq or bne instructions, only ? 215 distance
  can be specified.
• To jump to further instructions
• beq t0, t1, L1
• ...
• L1
• j L2
• ...
• L2

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Memory Addressing Modes

• direct
• memaddress
• register indirect
• memcontentreg
• memcontentaddress
• register indirect displacement
• memcontentregdisplacement
• memcontentaddressdisplacement
• register indirect index and displacement

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MIPS Addressing Modes

• Register addressing (R-format)
• add t0,t1,t2
• Base (Displacement) addressing (I-format)
• lw t1, 12(t2)
• Immediate addressing (J-format)
• addi t0, t1, 34

op rs rt rd funct
register
memory
op rs rt address

register
op rs rt Immediate data
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MIPS Addressing Modes

• PC-relative addressing (I-format)
• beq t0, t1, label
• Pseudo-direct addressing
• j label

memory
op rs rt address

PC
op address

PC