The Microprocessor and

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Tutorial 11

• The Microprocessor and
• its Architecture

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Objectives

• Revision on lecture note(CPU Architecture)
• Intel x86

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CPU

• What is CPU?
• one central unit that executes program
  instructions
• communicates with and controls the operation of
  other subsystems within the computer
• its main function to fetch and execute
  instructions

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CPU
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CPU Fundamental

• As you know, fetching and execution are broken
  down into smaller steps(e.g. movement between
  registers, addition by using ALU, etc)
• Each of these smaller steps is a machine code,
  i.e. an assembly instruction
• Assembly program will be assembled to machine
  instructions and then put in the main memory (You
  should know that already, Right?)

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CPU Fundamental

• Depends on the machine instruction, the CPU will
  generate a set of control signals to control
  other subsystem
• (You also known that)
• CPU bus(What is bus?)
• The bus is internal to the CPU
• connected the components in the CPU
• (e.g. ALU, GPR, MAR, MDR, PC, )

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CPU
Memory Function Completion indicates the
operation in memory is completed
CPU with Single-bus
CPU internal bus
From control unit
To main memory
Y,Z and TEMP are registers. That are transparent
to programmers. CPU will use it by itself.
From control unit
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Example of Bus organization

• Fetch a Word from MM
• Assume the address of the memory location to be
  accessed is in R1 and the memory data are to be
  loaded into R2
• Write a Word to MM

1. MAR lt R1
2. Read (control to memory)
3. Wait for MFC from memory
4. R2 lt MDR
CPU idle
1. MAR lt R1
2. MDR lt R2, Write signal to control
3. Wait for MFC from memory
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Control signals

• To MM
• Read, Write, Reset, etc
• To Registers
• Riin input data to Ri from CPU bus if 1
• Riout output data in Ri to CPU bus if 1
• 0 bus is used by others
• reset, etc
• To ALU
• Add, Sub, Mul, Div, etc

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Example of Control Signals

• Add data in R1 and R2 registers and
• put the result to R3

1. R1out,Yin
2. R2out, Add, Zin
3. Zout, R3in
Electronic switch In control 1 will get input
else will not Out control 1 will output the
data else 0 will not
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1-bit register with Switch
Z means the tri-state is in high impedance mode
Control to SR latch
SR latch (God! What is it?)
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Control Sequence

• ADD A,R1

1. PCout,MARin, Read, Clear Y, Set carry-in to ALU, Add, Zin Load PC into MAR Send Read request to the memory Reset Y to all 0s Load PC, 0 to ALU inputs, operate PC1 and write result to Z
2. Zout,PCin, WMFC Load Z to PC wait for memory to complete
3. MDRout,IRin Got data in MDR from MM and load it to IR
4. IRout,MARin, Read Load address of A to MAR Send Read request to the memory
5. R1out,Yin, WMFC Load R1 to Y and further to ALU wait for memory to complete
6. MDRout,Add,Zin Got data in MDR from MM and load it to ALU, add it to Y, and write result to Z
7. Zout,R1in,End Load Z to R1
Fetch
Execution
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Control Sequence

• BRN(conditional/unconditional)

1. PCout,MARin, Read, Clear Y, Set carry-in to ALU, Add, Zin Load PC into MAR Send Read request to the memory Reset Y to all 0s Load PC, 0 to ALU inputs, operate PC1 and write result to Z
2. Zout,PCin, WMFC Load Z to PC wait for memory to complete
3. MDRout,IRin Got data in MDR from MM and load it to IR
4. PCout, Yin Load branch address to Y and further to ALU
5. IRout, Add, Zin Load IR to ALU and add it to Y, put the result to Z
6. Zout,PCin,End Load Z to PC
For step 4, if not satisfy branch condition, then
End branch address PC Offset
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CPU with 3 internal buses

• required significantly fewer control steps
• ADD R1,R2,R3 (one clock cycle)
• execution phase to be performed in one
• clock cycle
• Y is not required because ALU can take two
• inputs from two registers from two data buses
• Z is not required because ALU can write the
• result to the destination register by 3rd bus
• performs register-to-register operations in
• a single clock cycle

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CPU Architecture
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Control Signal

• But how to generate the control signals as the
  control sequence discussed before?
• By microprogramming
• What is microprogramming?
• Using a sequence of microinstructions to
  generates a sequence of control signals

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Microprogramming

• A control word(CW) is a word whose individual
  bits represent the various control signals
• Each CW represents a set of control signals in
  one step of control sequence of an instruction,
  which is called microinstruction
• A sequence of CWs, which is referring to the
  control sequence of a machine instruction, is
  called microroutine
• Microprogram memory contains the microroutine of
  all instructions
• Depends on IR, a starting address of
  corresponding microroutine is given to
  microprogram counter
• MicroPC will be incremented and then a sequence
  of CWs will be given out

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Hand-shaking with Memory

• In the control sequence, there are steps that
  have to wait for MFC from memory. A signal WMFC
  is used.

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Hand-shaking with Memory

• Why MR?
• if
• But, if it starts at (i1)-th pulse,
• However, after the drop of (i1)-th pulse and
• before the raise of (i2)-th pulse,
• It is wrong!

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80x86
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8086 (Review)

• 16-bit processor with 20-bit address bus
• Direct mode addressing with memory space of
  1MByte
• 14 words by 16-bit register set
• (You should be familiar with them)
• Byte addressable
• For address and data operands, the least
  significant byte of the word is stored in the
  lower valued address location and the most
  significant byte in the next higher address
  location

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8086 (Review)
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8086

• Why there is no Program Counter(PC)?
• How to indicate the next instruction to be
  executed?
• How stack works?
• What is the function of SP?
• What is the starting position of SP?
• How CALL works?
• How to jump to other procedure?
• How to return(RET) to previous procedure?