William%20Stallings%20Computer%20Organization%20and%20Architecture%207th%20Edition

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William Stallings Computer Organization and
Architecture7th Edition

• Chapter 13
• Reduced Instruction Set Computers

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Major Advances in Computers(1)

• The family concept
• IBM System/360 1964
• DEC PDP-8
• Separates architecture from implementation
• Microporgrammed control unit
• Idea by Wilkes 1951
• Produced by IBM S/360 1964
• Cache memory
• IBM S/360 model 85 1969

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Major Advances in Computers(2)

• Solid State RAM
• (See memory notes)
• Microprocessors
• Intel 4004 1971
• Pipelining
• Introduces parallelism into fetch execute cycle
• Multiple processors

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The Next Step - RISC

• Reduced Instruction Set Computer
• Key features
• Large number of general purpose registers
• or use of compiler technology to optimize
  register use
• Limited and simple instruction set
• Emphasis on optimising the instruction pipeline

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Comparison of processors
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Driving force for CISC

• Software costs far exceed hardware costs
• Increasingly complex high level languages
• Semantic gap
• Leads to
• Large instruction sets
• More addressing modes
• Hardware implementations of HLL statements
• e.g. CASE (switch) on VAX

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Intention of CISC

• Ease compiler writing
• Improve execution efficiency
• Complex operations in microcode
• Support more complex HLLs

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Execution Characteristics

• Operations performed
• Operands used
• Execution sequencing
• Studies have been done based on programs written
  in HLLs
• Dynamic studies are measured during the execution
  of the program

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Operations

• Assignments
• Movement of data
• Conditional statements (IF, LOOP)
• Sequence control
• Procedure call-return is very time consuming
• Some HLL instruction lead to many machine code
  operations

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Weighted Relative Dynamic Frequency of HLL
Operations PATT82a
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Operands

• Mainly local scalar variables
• Optimisation should concentrate on accessing
  local variables

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Procedure Calls

• Very time consuming
• Depends on number of parameters passed
• Depends on level of nesting
• Most programs do not do a lot of calls followed
  by lots of returns
• Most variables are local
• (c.f. locality of reference)

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Implications

• Best support is given by optimising most used
  and most time consuming features
• Large number of registers
• Operand referencing
• Careful design of pipelines
• Branch prediction etc.
• Simplified (reduced) instruction set

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Large Register File

• Software solution
• Require compiler to allocate registers
• Allocate based on most used variables in a given
  time
• Requires sophisticated program analysis
• Hardware solution
• Have more registers
• Thus more variables will be in registers

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Registers for Local Variables

• Store local scalar variables in registers
• Reduces memory access
• Every procedure (function) call changes locality
• Parameters must be passed
• Results must be returned
• Variables from calling programs must be restored

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Register Windows

• Only few parameters
• Limited range of depth of call
• Use multiple small sets of registers
• Calls switch to a different set of registers
• Returns switch back to a previously used set of
  registers

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Register Windows cont.

• Three areas within a register set
• Parameter registers
• Local registers
• Temporary registers
• Temporary registers from one set overlap
  parameter registers from the next
• This allows parameter passing without moving data

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Overlapping Register Windows
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Circular Buffer diagram
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Operation of Circular Buffer

• When a call is made, a current window pointer is
  moved to show the currently active register
  window
• If all windows are in use, an interrupt is
  generated and the oldest window (the one furthest
  back in the call nesting) is saved to memory
• A saved window pointer indicates where the next
  saved windows should restore to

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Global Variables

• Allocated by the compiler to memory
• Inefficient for frequently accessed variables
• Have a set of registers for global variables

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Registers v Cache
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Referencing a Scalar - Window Based Register File
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Referencing a Scalar - Cache
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Compiler Based Register Optimization

• Assume small number of registers (16-32)
• Optimizing use is up to compiler
• HLL programs have no explicit references to
  registers
• usually - think about C - register int
• Assign symbolic or virtual register to each
  candidate variable
• Map (unlimited) symbolic registers to real
  registers
• Symbolic registers that do not overlap can share
  real registers
• If you run out of real registers some variables
  use memory

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Graph Coloring

• Given a graph of nodes and edges
• Assign a color to each node
• Adjacent nodes have different colors
• Use minimum number of colors
• Nodes are symbolic registers
• Two registers that are live in the same program
  fragment are joined by an edge
• Try to color the graph with n colors, where n is
  the number of real registers
• Nodes that can not be colored are placed in memory

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Graph Coloring Approach
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Why CISC (1)?

• Compiler simplification?
• Disputed
• Complex machine instructions harder to exploit
• Optimization more difficult
• Smaller programs?
• Program takes up less memory but
• Memory is now cheap
• May not occupy less bits, just look shorter in
  symbolic form
• More instructions require longer op-codes
• Register references require fewer bits

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Why CISC (2)?

• Faster programs?
• Bias towards use of simpler instructions
• More complex control unit
• Microprogram control store larger
• thus simple instructions take longer to execute
• It is far from clear that CISC is the appropriate
  solution

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RISC Characteristics

• One instruction per cycle
• Register to register operations
• Few, simple addressing modes
• Few, simple instruction formats
• Hardwired design (no microcode)
• Fixed instruction format
• More compile time/effort

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RISC v CISC

• Not clear cut
• Many designs borrow from both philosophies
• e.g. PowerPC and Pentium II

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RISC Pipelining

• Most instructions are register to register
• Two phases of execution
• I Instruction fetch
• E Execute
• ALU operation with register input and output
• For load and store
• I Instruction fetch
• E Execute
• Calculate memory address
• D Memory
• Register to memory or memory to register operation

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Effects of Pipelining
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Optimization of Pipelining

• Delayed branch
• Does not take effect until after execution of
  following instruction
• This following instruction is the delay slot

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Normal and Delayed Branch
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Use of Delayed Branch
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Controversy

• Quantitative
• compare program sizes and execution speeds
• Qualitative
• examine issues of high level language support and
  use of VLSI real estate
• Problems
• No pair of RISC and CISC that are directly
  comparable
• No definitive set of test programs
• Difficult to separate hardware effects from
  complier effects
• Most comparisons done on toy rather than
  production machines
• Most commercial devices are a mixture

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Required Reading

• Stallings chapter 13
• Manufacturer web sites