EE 319K Introduction to Embedded Systems

1
EE 319KIntroduction to Embedded Systems

• Lecture 5 Periodic Timer Interrupts,
  Digital-to-Analog Conversion, Sound, Lab 5

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Agenda

• Interrupt Basics
• Periodic Interrupts
• Digital to Analog Conversion
• Nyquist Theorem
• Sound generation

SysTick ISR
Output one value to DAC
3
Interrupts

• An interrupt is the automatic transfer of
  software execution in response to a hardware
  event (trigger) that is asynchronous with current
  software execution.
• external I/O device (like a keyboard or printer)
  or
• an internal event (like an op code fault, or a
  periodic timer.)
• Occurs when the hardware needs or can service
  (busy to done state transition)

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Interrupt Processing
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ARM Cortex-M Interrupts

• Each potential interrupt source has a separate
  arm bit
• Set for those devices from which it wishes to
  accept interrupts,
• Deactivate in those devices from which interrupts
  are not allowed
• Each potential interrupt source has a separate
  flag bit
• hardware sets the flag when it wishes to request
  an interrupt
• software clears the flag in ISR to signify it is
  processing the request
• Interrupt enable conditions in processor
• Global interrupt enable bit, I, in PRIMASK
  register
• Priority level, BASEPRI, of allowed interrupts (0
  all)

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Interrupt Conditions

• Four conditions must be true simultaneously for
  an interrupt to occur
• Arm control bit for each possible source is set
• Enable interrupts globally enabled (I0 in
  PRIMASK)
• Level interrupt level must be less than BASEPRI
• Trigger hardware action sets source-specific
  flag
• Interrupt remains pending if trigger is set but
  any other condition is not true
• Interrupt serviced once all conditions become
  true
• Need to acknowledge interrupt
• Clear trigger flag or will get endless
  interrupts!

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Interrupt Processing

• The execution of the main program is suspended
• the current instruction is finished,
• suspend execution and push 8 registers (R0-R3,
  R12, LR, PC, PSR) on the stack
• LR set to 0xFFFFFFF9 (indicates interrupt return)
• IPSR set to interrupt number
• sets PC to ISR address
• The interrupt service routine (ISR) is executed
• clears the flag that requested the interrupt
• performs necessary operations
• communicates using global variables
• The main program is resumed when ISR executes BX
  LR
• pulls the 8 registers from the stack

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Registers
R0-R3 parameters R4-R11 must be saved
R14, R15 are important
SP (R13) refers to PSP or MSPWe will use just
the MSP
PRIMASK has intr. enable (I) bit BASEPRI has
allowed intr. priority
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Priority Mask Register
Disable interrupts (I1)
CPSID I
Enable interrupts (I0)
CPSIE I
MRS R0,PRIMASK
CPSID I
MRS PRIMASK,R0
Interface latency
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Program Status Register

• Accessed separately or all at once

Q Saturation, T Thumb bit
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Interrupt Program Status Register (ISPR)
Run debugger - stop in ISR and - look at IPSR
12
Interrupt Context Switch
Vector address for GPIO Port C
Interrupt Number 18 corresponds to GPIO Port C
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Lab 6 Lab 8 Lab 9
77 total
INTERRUPT VECTORS
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Nested Vectored Interrupt Controller (NVIC)

• Hardware unit that coordinates among interrupts
  from multiple sources
• Define priority level of each interrupt source
  (NVIC_PRIx_R registers)
• Separate enable flag for each interrupt source
  (NVIC_EN0_R and NVIC_EN1_R)
• Interrupt does not set I bit
• Higher priority interrupts can interrupt lower
  priority ones

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NVIC Registers

• High order three bits of each byte define
  priority

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NVIC Interrupt Enable Registers

• Two enable registers NVIC_EN0_R and NVIC_EN1_R
  
• Each 32-bit register has a single enable bit for
  a particular device
• NVIC_EN0_R control the IRQ numbers 0 to 31
  (interrupt numbers 16 47)
• NVIC_EN1_R control the IRQ numbers 32 to 47
  (interrupt numbers 48 63)

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Interrupt Rituals

• Things you must do in every ritual
• Initialize data structures (counters, pointers)
• Arm (specify a flag may interrupt)
• Configure NVIC
• Enable interrupt (NVIC_EN0_R)
• Set priority (e.g., NVIC_PRI1_R)
• Enable Interrupts
• Assembly code CPSIE I
• C code EnableInterrupts()

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Interrupt Service Routine (ISR)

• Things you must do in every interrupt service
  routine
• Acknowledge
• clear flag that requested the interrupt
• SysTick is exception automatic acknowledge
• Maintain contents of R4-R11 (AAPCS)
• Communicate via shared global variables

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Interrupt Events

• Respond to infrequent but important events
• Alarm conditions like low battery power
• Error conditions
• I/O synchronization
• Trigger interrupt when signal on a port changes
• Periodic interrupts
• Generated by the timer at a regular rate
• Systick timer can generate interrupt when it hits
  zero
• Reload value frequency determine interrupt rate
  

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Synchronization
Use global variable to communicate

• Semaphore
• One thread sets the flag
• The other thread waits for, and clears
• Mailbox to be presented for Lab 7
• FIFO queue to be presented for Lab 8

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Periodic Interrupts

• Data acquisition samples ADC
• Lab 8 will sample at a fixed rate
• Signal generation output to DAC
• Audio player (we use the Systick interrupt to
  write samples out periodically in Lab 5)
• Communications
• Digital controller
• FSM
• Linear control system

Demo PeriodicSystickInts_4F120 and Periodic32bitT0
Ints_4F120
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Digital Representation of Analog Signals

• Digitization Amplitude and time quantization

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Conversion from Digital to Analog

• Range
• 0 to 3.3V
• Resolution
• 3.3V/15 0.22V
• Precision
• 4 bits
• 16 alternative
• Speed
• Monotonic

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Digital ? Analog Conversion
Sampled at a fixed time, Dt
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Digital ? Analog Conversion
Digital in voltage and in time
fs 1/Dt Signal has frequencies 0 to ½ fs
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Digital-to-Analog Converter (DAC)

• Binary Weighted DAC
• One resistor for each bit of output
• Resistor values in powers of 2

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3 bit DAC
R2 10 k?
R1 20 k?
R0 40 k?
n PB2 PB1 PB0 kohm equation Vout (V)
0 0 0 0 0.000
1 0 0 3.3 R2R1 6.67 3.3(R1R2)/(R0R1R2) 0.471
2 0 3.3 0 R2R0 8.00 3.3(R2R0)/(R1R2R0) 0.943
3 0 3.3 3.3 R1R0 13.33 3.3R2/(R2R1R0) 1.414
4 3.3 0 0 R1R0 13.33 3.3(R1R0)/(R2R1R0) 1.886
5 3.3 0 3.3 R2R0 8.00 3.3R1/(R1R2R0) 2.357
6 3.3 3.3 0 R2R1 6.67 3.3R0/(R0R2R1) 2.829
7 3.3 3.3 3.3 3.300
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Other Types of DACs

• R-2R Ladder DAC
• Binary weighted cascading ladder
• Improved precision owing to ability to select
  resistors of equal value

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DAC Performance

• Resolution, range, precision
• Maximum sampling frequency
• Monotonicity
• Input increase causes output increase (always)

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Resistor Network for 4-bit DAC
R3
R2
R1
R0
31
Dynamic testing
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Sound

• Loudness and pitch
• Controlled by amplitude and frequency
• Humans can hear from about 25 to 20,000 Hz.
• Middle A is 440 Hz
• Other notes on a keyboard are determined
• 440 2N/12, where N is no. of notes from middle
  A.
• Middle C is 261.6 Hz.
• Music contains multiple harmonics

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Tempo
Tempo defines note duration Quarter note 1
beat 120 beats/min gt ½ s duration
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Chord

• Two notes at the same time
• Superimposed waveforms
• 262 Hz (low C) and a 392 Hz (G)

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Instrument Characteristics
Waveform shape of a trumpet sound
Plucked string signal with envelope
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Synthesizing Digital Music

• Nyquists Sampling Theorem
• We can reproduce any bandlimited signal from its
  samples if we sample correctly and at a
  frequency, fs, that is at least twice the highest
  frequency component of the signal, fmax.
• Where do we get the samples?
• We could sample a series of musical tones
• We can compute the samples

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Synthesizing Digital Music (cont.)

• What is a musical tone?
• A sinusoid of a particular frequency
• Notes vary by twelfth root of 2 1.059
• What would the samples be?
• Fixed point numbers
• How do we generate a sinusoid?
• Output appropriate digital values via a resistor
  network that effectively produces an
  pseudo-analog signal
• What about frequency?
• Employ a programmable timer to tell us when to
  output the next value

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Synthesizing Digital Music (cont.)

• 440 Hz sine wave generated by 6-bit DAC

Frequency spectrum
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Music Generation Lab 5

• Objectives
• Employ LM4F/TM4C to generate appropriately scaled
  digital outputs at a specified frequency
• Three frequencies are required
• Frequencies are to be determined by switch
  settings
• Four digital outputs are inputs to a resistor
  network that serves as a digital-to-analog
  converter (DAC)
• Four output bits gt 16 levels
• Read the key (buttons) using Interrupts.

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Music Generation (cont.)

• DAC hardware
• Employ least significant four bits of a GPIO port
• Arrange resistor network in 1, 2, 4, 8 sequence
• Each port bit can assume digital levels of 0 and
  3.3 V
• Ports are current limited max 8 mA

R3
R2
R1
R0
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Music Generation (cont.)

• DAC software
• Interactions via device drivers
• Two device driver functions required
• void DAC_Init(void) // initializes the
  device
• void DAC_Out(unsigned char data) //
  transfers data to device
• (Device driver provides the functions associated
  with the device but hides the detailed actions
  necessary to implement the functions.)

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Music Generation (cont.)

• Interpretation of data
• Note has three parameters
• Amplitude (loudness)
• Frequency (pitch)
• Duration
• Amplitude is a digitally approximated sinusoid
• Sinusoid varies between 0 and 3.3 volts
• Frequency is selected by switches
• Four states stop, note_1, note_2, and note_3
• Duration is period switch(es) activated

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4-bit Sinusoid Table
SinTab 8,9,11,12,13,14,14,15,15,15,14
14,13,12,11,9,8,7,5,4,3,2
2,1,1,1,2,2,3,4,5,7
32 value sinusoid
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Musical Notes
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Tone Generation

• unsigned long I
• // 4-bit 32-element sine wave
• const uint8_t wave32
• 8,9,11,12,13,14,14,15,15,15,14
• 14,13,12,11,9,8,7,5,4,3,2
• 2,1,1,1,2,2,3,4,5,7
• For a 440Hz tone
• Assume a bus clock frequency of 50 MHz
• SysTick count every 20ns
• Each cycle of the 440 Hz sinusoid requires
• (50106 counts/s)/440 Hz 113636.36 SysTick
  counts
• Each cycle consists of 32 values each of
  duration
• 113636.36 interrupt counts/32 values 3551
  SysTick counts/value
• DAC values change every 71.02 us

SysTick ISR
Output one value to DAC
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Lab 5 ISRs

• Each Systick interrupt
• Output one value from the array to DAC
• Increment index to array (wrap back to zero)
• In main program
• If a switch (current key) is pressed set SysTick
  period (arm)
• If no switches are pressed then disarm

GPIO ISR
SysTick ISR
Note the Key Pressed
Output one value to DAC
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Other Instruments
// 6-bit 64-element bassoon wave const uint8_t
Bassoon64 33,37,37,36,35,34,34,33,31,30,2
9, 30,33,43,58,63,52,31,13,4,5,10,16,
23,32,40,46,48,44,38,30,23,17,12,11,
15,23,32,40,42,39,32,26,23,23,24,25,
25,26,29,30,31,32,34,37,39,37,35,34,
34,34,33,31,30 // 6-bit 64-element guitar
wave const uint8_t Guitar64
20,20,20,19,16,12,8,4,3,5,10,17,
26,33,38,41,42,40,36,29,21,13,9,
9,14,23,34,45,52,54,51,45,38,31,
26,23,21,20,20,20,22,25,27,29,
30,29,27,22,18,13,11,10,11,13,13,
13,13,13,14,16,18,20,20,20