:: Pre-Final Presentation 2-D Discrete Cosine Transform - PowerPoint PPT Presentation

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:: Pre-Final Presentation 2-D Discrete Cosine Transform

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Marketing Why DCT? ... New Product Proposal TaxiCab Advertising Author: Computing Services Last modified by: david kim Created Date: 11/6/2003 11:15:49 PM – PowerPoint PPT presentation

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Title: :: Pre-Final Presentation 2-D Discrete Cosine Transform


1
Pre-Final Presentation 2-D Discrete Cosine
Transform
  • Team Paradigm (Group M2)
  • Tommy Taylor
  • Brandon Hsiung
  • Changshi Xiao
  • Bongkwan Kim
  • Project Manager Yaping Zhan

2
Team Paradigm
3
2DDCT LVS result
4
2DDCT Layout
5
Poly Active
6
Metal 1
7
Metal 2
8
Metal 3
9
Metal 4
10
Total area 450 x 440Aspect ratio 1.02Transist
ors 35140Density 0.18
11
Problem with 1DDCT SPICE simulation
  • Do not reach full power rails, only about 1.1 v.
  • Tried increased metal width and substrate
    contact, didnt solve the problem.
  • Need to bread down big modules and do SPICE
    separately to pin down the problem.

12
Agenda For Final Presentation
  • Title slide
  • Introduction (Tommy)
  • Marketing Strategy (Tommy)
  • The game plan (Tommy)
  • Algorithm (Changshi)
  • Original estimates (Changshi)
  • Designing the chip (Changshi)
  • Verification (Bongkwan)
  • Problems encountered (Bongkwan)
  • Final chip design and specs (Bongkwan)
  • Layout (Brandon)
  • Conclusion (Brandon)
  • Emulations (Brandon)
  • Total 37 Slides

13
Introduction
  • Introductory video clip
  • Description of project
  • What is a DCT?

3 Slides
14
Marketing
  • Why DCT?
  • Applications

2 Slides
15
Algorithm
  • Description of algorithm
  • How it works
  • Flow diagram

Game Plan
4 Slides
  • Design and chip goals

16
Original estimates
  • Chip layout
  • Floorplan
  • Transistor count
  • Pie chart
  • Size of major components
  • Table
  • Total chip area

4 Slides
17
Designing the chip
  • Process from description to implementation
  • Flowchart
  • Major changes in components
  • Changes in floor plan
  • Animated schematics

5 Slides
18
Verification
  • Behavioral
  • Logic
  • Schematic
  • Layout
  • Spice

3 Slides
19
Problems encountered
  • Problems during behavioral and logic testing
  • Problems with Schematic
  • Problems with layout
  • Problems with spice

4 Slides
20
Final chip design and specs
  • Total chip area
  • Size of major components
  • Total transistor count
  • Transistor count of major components
  • Pin specs

2 Slides
21
Layout
  • Layer masks
  • Poly/active, m1,m2,m3,m4
  • Full layout
  • Full layout w/ overlaid floor plan
  • Animation overlays floor plan on full layout

6 Slides
22
Conclusion
  • Why is our chip special
  • Lessons learned

1 Slide
23
Emulations
  • C code
  • Matlab

2 Slides
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