Data I/O Azido

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Data I/O Azido
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How Do You Square a Number?
y x2

• Did you consider the data types for x and y?
• Floating point? Fixed point? Complex?
• Are x and y the same or different?
• Did you consider the sizes of x and y?
• Are x and y the same or different?
• Do you care?

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An Often Forgotten Truth

• Algorithms are different from implementations
• Algorithms are relatively easy to re-use and to
  port to a different technologies
• Implementations are often too specific to a
  particular technology to re-use

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Azido and Mang Ren Mo Xiang(The Blind Men and
the Elephant)
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Azido

• Purpose-designed to rapidly develop and test
  high-performance computer applications
• High-level graphical design capture system
• Leverages object-oriented programming (OOP)
  techniques
• Intuitively capture natively parallel operations
• Tune algorithms for maximum performance or
  minimum resources (or somewhere between)
• Fast and efficient solver that directly maps to
  logic
• Adaptable to various CPU/FPGA boards and systems

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Azido

• Integrated, immersive, test-on-the-fly simulation
  and hardware test integration
• Rapidly develop and prototype on x86 platform
• Interact with real application running in
  hardware
• Leverages FPGA vendor tools to place and route
  designs
• Azido designs can be ported to other hardware
  architectures with the least amount of effort,
  time, and change to the design

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Bridges to Traditional Environments

• EDIF Translation/Conversion
• EDIF ? Azido
• Azido ? EDIF
• API Calls
• COM/Active-X module interfaces

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Azido Adjectives

• Graphic
• Drag-and-drop
• Interactive, instantaneous debugging
• Object-oriented
• Technology independent
• Inherently parallel
• Flexible data sizes, types, and precision
• Recursion
• Overloading
• Underloading

• Correct by construction
• Code re-use
• Sequential vs. parallel trade-offs
• Polymorphism
• IP re-use

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Azidos Proud Pedigree

• Descendant of Star Bridge Systems Viva

• Star Bridge HAL300 Hypercomputer
• 200 FPGAs
• 720 memory channels
• Kirchhoff pre-stack time migration

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Azido ExampleCantilever Beam Optimization
Constants L 24 W 3 P 20 lbs
0.097 lbs/in3 Constraint Stressallowed 40K
lbs/in2
Find thickness, d, to minimize
where
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Azido/FPGA Minimizes Beam Weight
Azido Results d 0.156 (0.155 exact) Minimum
weight 1.09 lbs (1.082 exact)
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Azido Design Cycle
Design Entry/Algorithm Implementation
Synthesis
Build In Hardware
Stage 1
Stage 2
Includes Device Drivers Interface to C/COM
System simulation Test harness System harness
FPGA-based Hardware
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Azido Design Flow
Rapid Development Environment
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Azido Abstraction Layers
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Azido Overview

• Quickly Building an Example System
• User Interface
• Azido Primitives and Transports
• Data Sets and Types
• Object Recursion
• CoreLib Core Library
• Data Flow Control and Synchronization
• System Descriptions
• Interactive Debugging
• Next Steps

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An Example SystemQuickly Built with Azido

• Machine vision and tracking system

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Hardware Demo Counter

• A simple binary counter with variable count value
• Build and test in x86
• Implement and test on Xilinx Spartan-3 XC3S4000
  FPGA (Opal Kelly board)

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Opal Kelly XEM3050 Board
http//www.opalkelly.com/products/xem3050/
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EVB1005 Camera Board

• Aptina CMOS imager
• Directly connects to back of XEM3050 board

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System Block Diagram
Histogram
CMOS Imager
Aptina Camera Frame Grabber
Bayer Pattern to RGB Converter
White Balance
RGB to Gray Converter
Segment-ation
Blob Feature Extraction
Blob Filter
Write Frame
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Bayer Camera Image Processing

• Camera output is not traditional RGB
• Uses Bayer pattern (more green sensitivity)

Interpolating Red and Blue Four cases
Interpolating Green Two cases
Bayer Pattern
www.siliconimaging.com/RGB20Bayer.htm
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Azido User Interface

• A Brisk Walk Through the Environment

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Azido User Interface
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• Add/Delete/View sheets within project
• Name/Rename sheets

• Drag/Drop objects onto sheet
• Examples on object use
• Contains polymorphic modules and objects to be
  used in designs and applications, e.g. Logic
  Gates, Registers, Shifters, Math operators

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• Red Text Error
• Black Text Warning
• Blue Text Information
• Green Text User Trap
• Error Log file placed in Project directory

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• Search for objects within CoreLib using (Ctrl
  F)
• Search is based on a literal character match
• No wildcard characters allowed
• Search window displays all the locations where
  the object is present within the project
• Navigate to the object by double-clicking the
  entry in the search window

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• Displays the various overloads available for an
  object.
• Ctrl Double click an object to view its
  overloads

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I2ADL Editor (Implementation Independent
Algorithm Description Language)

• Create/Edit and document applications and objects
  in Azido
• Add/Edit functionality of sheets and objects
• Create/Modify library components

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• View/Edit/Create datasets to be used in Azido
• View child datasets of parent datasets
• Modify color codes for different datasets

Dataset Editor
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• View/Edit resources within FPGA-based System
• Displays the resources used by a particular
  application build

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• Define Build options and locations of build files
  within the project directory
• Define different options to the vendors PAR tool
  for the design
• Starting point for creating and editing system
  descriptions

System Editor
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• Adjust the clock speed depending on the
  constraints and complexity of the algorithm being
  implemented

• Objects and libraries created in Azido support
  high clock speeds, removing one more barrier for
  an application designer.

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Azido Primitives and Transports

• Start with the Basics

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Primitives Fundamental Units

• Primitive library loaded automatically
• Basic bit-oriented Boolean functions
• AND
• OR
• INVERT
• Atomic-level functions
• Cannot be broken down further

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An Analogy From Simplicity to Complexity
Primitives
u
Up Quark
d
Down Quark
e
Electron
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Transport is also a Primitive

• A peer to the other primitives
• Moves data from a source to one or more places
• As simple as data move operation
• As complex as a COM interface call
• Moves bits, buses, scalars, vectors, lists, etc.
• Interprocess communication, even between chips
  and systems

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Azido Data Sets and Types

• How Bits Become Systems

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Azido Fundamental Data Sets

• Azido allows clean separation between algorithm
  and implementation
• Bit The usual definitions (0/1, off/on,
  false/true)
• Variant Unknown data type at time of
  construction specified or resolved during
  synthesis
• List Collections of two or more data sets
  modeled on Lisp, Prolog

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The Power of Variants

• Implementation may differ, depending on the
  incoming data set
• Data set is defined during Azido synthesis

x2 x?x

• Algorithm remains the same, regardless of the
  data type

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Processor-based Systems
Bit

• Processors have fixed, pre-defined data sizes
• 8-, 16-, 32-, 64-bit
• IEEE floating point
• Single precision
• Double precision
• Consequently, so do
• programming languages
• operating systems

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Byte (char)
7
6
5
4
3
2
1
0
1
0
0
1
1
0
1
0
Integer
2
1
0
15
14
13
12
1
0
0
1
0
1
0
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FPGA-based Systems

• Field-Programmable Gate Array (FPGA) architecture
• Logic
• Memory
• Programmable connections
• I/O
• User-defined application architecture
• Flexible, adaptable
• Inherently parallel
• Flexible data widths

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Azido Supports Multiple Data Sets

• Static

• Dynamic

• Mandated by the fixed architectures of
  processor-based systems
• Examples
• Nibble, Byte
• Int, Dint, Qint
• Word, Dword, Qword
• Float, Double
• Fix16, Fix32
• COM-based types

• Provides the freedom and richness available in
  FPGA architectures
• Five predefined dynamic sets
• Complex
• Fixed-point
• Floating
• Signed
• List

Or create your own!
Must always convert back to static when
communicating with fixed architecture
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Azido Dynamic Data Sets
Variant
Real
Complex
Any data set
Real
Imaginary
Imaginary
Any data set
Fixed
Sign, Whole Number
Fraction
Floating
Sign, Exponent
Mantissa
Exponent
Mantissa
Sign
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Azido Basic Data Sets
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Static Data Sets
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COM Object Data Sets
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Azido Shaped Data Sets

• MSB First (MSB)
• LSB First (LSB)
• Binary Tree (BIN)

• Same binary information, ordered differently
• Available in a variety of sizes
• Specify during synthesis

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Exposers and Collectors

• Manipulating Data Sets

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Exposers and Collectors

• Exposer Decompose a data set into its
  constituent data sets
• Collector Compose data sets into a single data
  set
• For those familiar with C, think of a data set
  as a struct

Collector
Exposer
Real
Complex
Real
Variant
Variant
Imaginary
Imaginary
struct Complex variant Real variant
Complex
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Object Recursion

• Second Verse, Same as the First

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Two Versions of INVERT Object

• INVERT Bit function

• Invert VARIANT function

• From Primitive Objects
• Bit input and output
• Atomic-level primitive
• Cannot be further reduced

• From CoreLib/Gates
• Variant input and output
• Must be further reduced during synthesis

Bit
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How is INVERT Defined?
Output recast to the same type as the Input
INVERT calls itself Recursion!
Variant
Variant
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Recursion Example

• What happens if you compile the following design
  for the Byte data set?

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Invert Byte (8 bits)
Nibble
Byte
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Invert Nibble (4 bits)
Nibble
Byte
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Invert Dbit (2 bits)
Nibble
Byte
Now resolve the output Collectors!
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Resolve Dbit (2 bits)
Resolving output Collectors
Nibble
Byte
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Resolve Nibble (4 bits)
Resolving output Collectors
Nibble
Byte
Nibble
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Resolve Byte (8 bits)
Done!
Nibble
Byte
Byte
Nibble
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INVERT Works for Other Data Types

• The same INVERT function works for other data
  sets
• From 1 to 128 bits
• Complex
• Fixed-Point
• Floating-Point
• Lists

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Azido Design Libraries

• CoreLib Simplifies Life

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CoreLib Core Library

• Reusable, flexible CoreLib library adds
  higher-complexity functions
• Math
• Control
• Data Conversion
• Memory
• Grammatical operations
• Polymorphicsupports various data sets and types
• Other advanced libraries available from
  developers
• DSP, etc.

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Azido Objects are Polymorphic

• Library objects adapt to input and output data
  sets
• Example Same multiply object handles scalars,
  vectors (Lists), floating point, fixed point,
  etc.

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CoreLib Arithmetic Operations

• Asynchronous Operations
• Not clocked
• No data flow control (coming up)

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Discover the Basics of an Element

• Right-click on an element to reveal
• Documentation
• Ports
• Description
• Attributes

Right-click
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CoreLib Arithmetic Operations

• Synchronous, clocked
• Data flow control (GDBW)

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CoreLib Comparators

• Both asynchronous and synchronous with flow
  control
• Minimum and Maximum functions

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CoreLib Encoders/Decoders
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CoreLib Gates
From 2 to 16 inputs
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CoreLib Grammatical Operations
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CoreLib Grammatical OperationsBit Length
Math/Compare
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CoreLib Converters
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Change the Library View
If in Tree view
If in Name view
Right click, Sort by Name
Right click, Sort by Tree
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Go-Done-Busy-Wait (GDBW)

• Synchronization and Data Flow Control

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Go-Done-Busy-Wait Control Flow

• Go-Done-Busy-Wait (GDBW) mechanism controls the
  data flow, synchronizations, and data sequencing
  of an application
• Fork and join
• Spring synchronization
• Back-pressure with differential latency
  compensation

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GDBW Flow Control Example
Go
Done
Go
Done
Go
Busy
Wait
Busy
Wait
Wait

• Function 1 has new data to propagate
• Downstream Function 2 is not busy and can accept
  new data

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GDBW Flow Control Example
Go
Done
Go
Done
Go
Busy
Wait
Busy
Wait
Wait

• If unable to complete in a single clock cycle,
  Function 2 signals Busy to upstream Function 1
  until it is Done
• Upstream Function 1 must not send new Go data
  untilFunction 2 is no longer Busy

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GDBW Flow Control Example
Go
Done
Go
Done
Go
Busy
Wait
Busy
Wait
Wait

• When finished, Function 2 signals Done to
  Function 3
• Function 2 also is no longer Busy and accepts
  new Go data from Function 1

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GDBW Flow Control Example
Go
Done
Go
Done
Go
Busy
Wait
Busy
Wait
Wait

• Even if Function 1 and 2 have new data, they
  must wait until Function 3 is no longer Busy
• Backpressure or Spring synchronization

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GD(BW) Synchronization

• Synchronization
• Multiple data paths
• Different process latency through different paths

Synchronize all Donesby creating a List
Only GO-DONE chain shown. BUSY-WAIT removed for
clarity.
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GDBW Synchronization
Add
Square Root
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GDBW Pipelining

• Pipelining
• Maximize efficiency
• Ensure data stability

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Azido Runtime Widget Interface

• Widgets provide visibility into design behavior
  both during simulation (x86) and real-time
  hardware
• Runtime widget provides ability to single-step
  through design using UseManualClk and
  ManualClk controls

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CoreLib Controllers
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Overloading
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Overloading

• Equivalent function overload
• Name space
• Number of inputs
• Symbol substitution constraint wavefront
  chain rule
• Underloading Moving from the general to the
  specific
• System Description provides specific options
• Redefines objects to work as system implements
  them

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System Descriptions

• Azidos Device Drivers

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System Descriptions
Azido Application
FPGA-based
Executes on both types of systems
XEM3050
XEM6110-LX45

• Describes the system on which the Azido design
  will execute
• Compute resources and types
• Communication
• Essentially, the device driver

and others
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System Descriptions x86

• Use the x86 SD to initially design and test the
  application
• Almost every object in CoreLib has an equivalent
  x86 SD for fast, interactive simulation
• Executes on the processor and provides accurate
  simulation of design ensuring successful
  place-and-route during synthesis

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System Descriptions HC

• Contains objects and system-level implementations
  mapped to specific components and primitives
  within FPGA system
• All Library objects and components contain
  equivalent descriptions for each FPGA SD
• Different SDs can be created using Azido for
  different FPGA-based systems from other vendors

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Interactive Debugging

• Runtime Widget Interface

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Debugging Within Azido

• All signals visible and interactive
• Attach input and output horns to transports
• Set traps on output horns to generate a message
  visible in the message window
• Interactively verify functionality using the x86
  system description
• Message window indicates nature of error/warning
  and the location of object where the error took
  place
• Error messages logged within Azido folder

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Azido Debugging Widgets

• ScrollBar
• Default widget
• TextBox
• SpinEdit
• Input only
• Button
• Graphs
• Output only
• Memo
• Output only
• Decimal/HexOutput

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Changing Widget Options

• Set Widget Type

• Decimal/hex options

• Right-click on widget
• Select Change To
• then select widget type

• Right-click on widget
• Select Toggle Hex Display

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Set Widget Options during Design

• SET Widget option

• Right-click on input or output horn
• Click on cell under Attributes
• Select Widget from drop list
• Click on adjacent cell under Values
• Select widget type from drop list
• Click OK to accept
• Must resynthesize to see effect

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Debugging

• There are two attributes which facilitate
  debugging in Azido
• Global
• Trap
• The Global attribute is used to create an output
  which is not necessarily recognized as part of
  the footprint of the object. Besides, it can also
  be used to create an implicit connection between
  the input of one object and the output of
  another.
• The Trap attribute is placed along with a
  message. The message is displayed whenever data
  is propagated to that output
• These attributes, when placed within the
  hierarchy of an object can be effectively used to
  observe outputs from within the hierarchy

Viewing low-level signal with ease
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Debugging Example

• Purpose
• To demonstrate debugging within Azido

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Next Steps

• Getting Started with Azido

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Get Started with Azido!

• Request access to Azido Beta site
• Download and install Azido development
  environment
• Azido runtime for Windows (and virtual machines)
• Xilinx ISE (optional, but required for hardware
  interaction)
• Learn about Azido
• Tell us what you think

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Questions?
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Thank You!

• (but we need the thumb drives back!)

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Additional Slides
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Type System

• Data Sets
• Graphical Representations
• Exposers and Collectors
• Context
• Separation of Size and Type
• Typecontext size variant
• Variant exposer collector data grammar
• Cast / convert /context

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Simple Exposer/Collector Example
List
Data Set Color Coding
Variant
Fixed
Compiled as Byte data set
ANSWER The Fixed data type does not exist in
the x86 architecture. Convert it to a List for
display.
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CoreLib Exposers/Collectors
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CoreLib MSB, LSB, BIN
From 2 to 36 connections
Packs or Unpacks bit lists into smaller,
equal-sized lists