EEL4930/5934 Reconfigurable Computing

1
EEL4930/5934 Reconfigurable Computing

• The state-of-the-art Reconfigurable Computing
  equipment available for this course is made
  possible by a generous grant from the Rockwell
  Collins Growth Relationship Grant Program and an
  equipment/software donation from Nallatech.

2
Instructors

• Dr. Greg Stitt
• gstitt_at_ece.ufl.edu
• http//www.gstitt.ece.ufl.edu
• Office Hours To be announced
• (Benton 323)
• Also, by appointment

3
Course Website

• 2 sites
• http//www.gstitt.ece.ufl.edu/courses/eel4930_5934
  /
• Linked off my website
• WebCT Vista/E-learning
• http//lss.at.ufl.edu/
• Select e-learning
• Login with GatorLink account
• Used for posting grades, turning in projects
• Email Policy
• When sending an email, include the class name in
  brackets
• e.g. EEL5934 Question about project 2

4
Grading

• EEL4930/5934 Grading
• Mid-term 1 30 (Dates to be announced)
• Mid-term 2 30
• Labs/Homework 10
• Project 30
• Final grade curved average of all components
• 5934 may possibly have different tests and project

5
Lab Assignments

• Linked off main website
• http//www.gstitt.ece.ufl.edu/courses/eel4930_5934
  /labs/
• Intended to familiarize with FPGA boards, VHDL
• Initial labs will be individual
• Will allow groups when using boards

6
Research Project

• Groups
• Size to be determined based on enrollment
• Likely 2-3 per group
• Topic subject to instructor approval
• Will give examples
• Good idea - find algorithm in your area, use RC
  to improve performance
• Imaging processing, bioinformatics, CAD, etc.
• If interested in research, make an appointment
  with me
• Will try to find a project that will helps
  towards degree

7
Reading Material

• Textbook The Design Warriors Guide to FPGAs
• C. Maxfield
• ISBN 978-0750677045
• Supplemented by research papers
• Check class website for daily requirements
• Will also post slides when used
• Optional books also listed in syllabus

8
Prerequisites

• You should be familiar with
• Digital design
• Architecture
• ControllerDatapath
• Memory Hierarchy
• Pipelining
• More listed in syllabus
• Assumes no knowledge of reconfigurable computing

9
Goals

• Understanding of issues related to RC
  (reconfigurable computing)
• Architectures
• Tools
• Design methodologies
• Speedup analysis
• Etc.
• Detailed investigation of a specific problem
• Research project
• Publish!
• Best projects will be submitted to conferences

10
Academic Dishonesty

• Unless told otherwise, labs and homework
  assignments must be done individually
• All assignments will be checked for cheating
• Groups must obtain permission to use larger size
• May be allowed for difficult projects
• Collaboration is allowed (and encouraged), but
  within limits
• Can discuss problems, how to use tools etc.
• Cannot show code, solutions, etc.
• Cheating penalties
• First instance - 0 on corresponding assignment
• Second - 0 for entire class

11
Attendance Policy

• Attendance is optional, but highly recommended
• If you are sick, stay at home!
• If obviously sick, you will be asked to leave
• Missed tests cannot be retaken, except with
  doctors note

12
What is Reconfigurable Computing?

• Reconfigurable computing (RC) is the study of
  architectures that can adapt (after fabrication)
  to a specific application or application domain
• Involves architecture, design strategies, tool
  flows, CAD, languages, algorithms

13
What is Reconfigurable Computing?

• Alternatively, RC is a way of implementing
  circuits without fabricating a device
• Essentially allows circuits to be implemented as
  software
• circuits are no longer the same thing as
  hardware
• RC devices are programmable by downloading bits -
  just like software

Microprocessor Binaries
FPGA Binaries (Bitfile)
Bits loaded into program memory
Bits loaded into CLBs, SMs, etc.
0010
0010
14
Why is RC important?

• Tremendous performance advantages
• In some cases, gt 100x faster than microprocessor
• Alternatively, similar performances as large
  cluster
• But smaller, lower power, cheaper, etc.
• Example
• Software executes sequentially
• RC executes all multiplications in parallel
• Additions become tree of adders
• Even with slower clock, RC is likely much faster
• Performance difference even greater for larger
  input sizes
• SW time increases linearly
• RC time is basically O(log2(n)) - If enough area
  is available

for (i0 i lt 16 i) y ci xi
15
Reminder

• Lab 0 - ISE Tutorial
• Read RC survey linked off website