ISPD - 2005 A New Era for CAD

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ISPD - 2005A New Era for CAD

• Gary Smith
• Chief Analyst
• Design Engineering

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The Automation of RTL Design 2005

• The IC Implementation Tool Set automated RTL
  input to GDS II
• The RTL Functional Verification Tool Suite
  automated RTL input to GDS II
• But GDS II is no longer sufficient.

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The Automation of the RTL Methodology (from
DQ_at_DAC 2005)
IC Implementation
RTL Verification
Intelligent Test Bench
Silicon Virtual Prototype
Moved to the ES Level
Just becoming Reality
Physical Synthesis
RTL Simulation
Formal Verification
DFT
Formal Analysis
Timing, Signal-Integrity and Power Analysis
Acceleration and Emulation
IC Place and Route
RTL Design Tools
GDS II
?
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The IC Implementation Toolset(from DQ_at_DAC 2002)

• This is the RTL to GDS II tool flow
• The functions within the toolset (as a minimum)
  include logic synthesis timing, signal-integrity
  and power analysis probably DFT and clock tree
  synthesis IC place and route (final route is
  being questioned by some ASIC vendors)
• The market has been all but wrapped up by
  Synopsys, Magma and Cadence

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What Happened ?
ESL
IC Implementation Tool Set
GDS II
DFM Correction IC re-Layout
Mask Shop
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But it Didnt Yield !!!

• The COT Crisis at 130 nm.- The August 2001
  awakening.
• Whos Responsible !!!- The Designer- The
  Foundry- The Mask Shop will fix it !
• But will they ?

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The Era of Disaggregation

• The 1990s were the Cream Puff era of
  Semiconductors.
• Plain old vanilla CMOS was king.
• Other processes, such as Silicon on Insulator and
  GaAs, were only niche players.
• Process improvements were all incremental.
• The Foundry model grew rapidly.
• The RTL Methodology drove design the entire
  decade.
• It was all so easy.

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Back to the Future !

• This Decade is looking more like the 1980s.
• Process RD and Device Physics are a vital part
  of an IDMs competitive profile.
• Will the Foundries be laggards ?
• Is this the end of CMOS, at least plain old
  vanilla CMOS ?
• What does the new transistor look like at 45 nm
  ?
• Engineers are moving up to the ES Level of design.

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Competitive Re-aggregation

• IDMs and Foundries are moving the Mask Shop back
  In-House.
• ASIC Vendors are doing a majority of the IC
  Layout In-House again.
• Twenty Seven Percent of the designers are using
  some In-House developed tools.
• Mainstream OEMs are looking for ASIC vendors to
  take an RTL design Hand-off.
• Is COT a shrinking business model ?
• Will the IDMs/Foundries buy up the DFM vendors to
  keep their new process information proprietary ?

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The Migration of Design Engineers
SoC Design Opportunities are Driven by
Applications
ESL
RTL
CAD
SoC Implementation Challenges are Driven by
Silicon
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Todays Challenges and Opportunities
ESL
DFM
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The IC Layout Team comes to the Rescue

• The Mask Shops are facing shrinking business and
  shrinking margins.
• The Design Team just learned circuit design they
  arent ready for Layout issues.
• The IC Layout team was supposed to go away with
  the new IC Implementation Tool Sets.
• Now they are the second fastest growing EE
  segment.

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The Migration of DFM Technology

• There are three DFM markets.- The Fab
  engineer- The IC Layout Engineer- The Design
  Engineer
• Tools for the FAB engineer will be a specific
  market, but fairly small. - And no they wont
  pay royalties.
• The IC Layout Engineer will be the main market.
• The Design Engineer will use tools that
  incorporate the last generation of DFM tools and
  methods.

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A New Era for CAD

• So CAD wont go away as expected.
• If the EDA industry provides the tools on
  time it will continue to be a growing market.
• If not the tools will increasingly be built
  In-House by the Semiconductor vendors.
• There is no reason to expect that the CAD market
  wont continue to supply tools once we enter the
  non-silicon era of Semiconductors.