Some Irradiation Results from a Chip in UMC018 Technology

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Some Irradiation Results from a Chipin UMC018
Technology

• Peter Fischer for Christian Kreidl
• Heidelberg University

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Summary

• UMC018 Chip was irradiated with X-rays to 7.5Mrad
• No degradation after annealing
• Strange effects around 1.2Mrad
• Work done in the frame of the DEPFET project
• Measurements by Christian Kreidl
• Chip by Ivan Peric

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The Chip

• DCD1 DEPFET Current Digitizer
• Readout Chip for DEPFET Sensor columns
  

DEPFET Sensor goes here
DCD1 Chip
current memory cells to subtract pedestal
8 bit ADCs using current memory cells
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More Details...
2 ADCs
ADC Output Logic
Current Subtract
Regulated Cascode
Sampling
Test Injection current
Generate ADC memory cell control signals
ADC result calculation, MUX
per pixel
3 x 6 lines
ADC Steering Signals
Serializer
Sample
Monitoring Pad
Clock Divider
600MHz
sync for FPGA, Switcher
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Chip Layout Design

• UMC 0.18µm technology, 2 x MiniASIC size
• ADC in radhard layout (enclosed NMOS, guard
  rings)
• Digital part without any precautions
• 72 inputs

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Pixel Layout
Size x 180µm Size y 110µm
regulated cascode
two 8 bit algorithmic current mode ADCs working
interleaved
digital stuff (conservative layout)
bump pad with 60µm opening
test injection
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Chip Test Setup

• Chip glued bonded to PCB no cover
• Readout via USB

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Irradiation Facility in Karlsruhe

• 60 keV X-Ray tube at Institut für Nuclear
  Physics, Karlsruhe
• 100-250 krad/h (depending on distance),
  calibrated setup
• Thanks to Dr. Simonis, Mr. Dierlamm and Mr.
  Ritter for help!

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Irradiation

• Dose
• 31h _at_99.5 krad/h (d180mm) 3.1 Mrad
• 18h _at_241 krad/h (d100mm) 4.4 Mrad
• Total 7.5 Mrad
• DCD Operation Mode
• clock running permanently
• control registers loaded every 30s with default
  values(precaution against SEU)
• Measurements (while tube is on!)
• current consumption on VDD ( analog digital)
• on selected pixels- Current memory cell
  operating range- ADC characteristics- Test
  injection current value

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Current consumption

• Total supply current (analog digital)
• Current rises until 1.2Mrad, then settles to
  pre-rad value

1.2Mrad
pre-rad
Probably bit flip In Bias DACs
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Current Memory Cells

• Cell keeps input voltage constant within 10µA

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ADC Characteristic (ADC value vs. Injection DAC)

• Test current injected via ON-CHIP injection DAC
• SEUs during measurement (more at 1.2Mrad !)
• most effects _at_lt1.2Mrad, some ADCs BROKEN
• after 7Mrad and 6 days annealing back to pre-rad
  behavior

Pixel 59
Pixel 71
BROKEN _at_ 1.2Mrad
0 Mrad after anneal.
7 Mrad
Many SEUs
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Test Injection Current vs. DAC value

• Test injection current is ok (not dead). Some
  variation.

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ADC Histograms

• Plot deviation from straight line
• 45nA (_at_0) ? 70nA (_at_1.2-7 Mrad) ? 44nA (7 day
  anneal)

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ADC noise map

• All ADCs back to initial values after anneal

Readout problems due to setup
Readout problems due to setup
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Summary

• No degradation after 7Mrad of 60keV X-rays
• Strange effects at 1.2 Mrad (power higher, ADC
  dead)

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Thank you!
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Bump Bonding Status in HD

• Peter Fischer, ziti, Uni Heidelberg
• for Christian Kreidl

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Reminder

• We do gold stud bumping
• Create a gold sphere on bonder
• Place ball on chip, Thermocompress, rip off wire
• Place all bumps
• Flip press heat (50g / bump)
• Can put bumps on both sides to reduce forces
• Can put isotropic glue with conducting particles
• Key parameters
• Diameter of balls 45µm
• Min. bond pad size 60µm
• Min pitch 100µm
• Advantages
• single chip (prototype) process, in house, cheap
• Drawbacks
• sequential, limited of pads, large force,
  possible destruction of electronics under pad,
  need hard substrate, no rework

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Tests with Dummy Chips

• Aluminum on Silicon structures
• Substrate and chip
• Trace pattern to check contact shorts

SuS_at_Uni-Heidelberg
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Chip with Bumps
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Flipped Assemblies

• 80g/bump all bumps connected, no shorts
• 20g/bump 4 of 6 snakes connected, chip fell off

SuS_at_Uni-Heidelberg
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Large Size Module

• Mechanical demonstrator of ILC vertex detector
  module
• no electrical tests
• check how to handle a large silicon device
• check how low pitch flipping works
• 16 DCD (dummy) chips
• 36 Switcher (dummy) chips
• 11,9 cm x 1,6 cm
• No electrical test possibilities

8 DCD chips
8 DCD chips
2 x 18 Switcher chips
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Placing Chips Close to Each Other (side view)

• Switcher (dummy) chips
• 164 bumps each1
• ,4mm x 5,8mm
• 60g/bump 9,8kg/chip

Edge of flip tool
SuS_at_Uni-Heidelberg
SuS_at_Uni-Heidelberg
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ILC Mechanical Sample
SuS_at_Uni-Heidelberg
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Minimum gap
50µm gap
50µm gap
SuS_at_Uni-Heidelberg
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Module End

• 224 bumps/chip, 1.35mm x 4.95mm, 13.4kg/chip

200µm gap
SuS_at_Uni-Heidelberg
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Full sample

• One module populated with 52 chips
• No failures !

SuS_at_Uni-Heidelberg
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Effort

• Bonding process cleaning, mounting, aligning,
  bumping
• Switcher 11min
• DCD 13min
• Flipping process pickup, aligning,
  thermocompression
• 9 min
• 2 days of work including learning
• Improvements
• build better mounting device for single chip
  bumping (mechanical clamp)

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Thank you!
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ADC Design in Heidelberg

• Peter Fischer, ziti, Uni Heidelberg
• ADC Design Ivan Peric

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Content

• Algorithmic / Pipeline ADC principles
• Voltage vs. Current Mode
• ADC in DEPFET readout chip
• Reminder ADC of David Muthers (Kaiserslautern)
• Comparison of figures of Merit

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Algorithmic (Cyclic) ADC

• Idea
• Compare signal to half scale ? generate BIT
• If BIT 1 subtract half scale
• Multiply result by two
• Restart over again
• Every cycle produces a new bit
• Very popular architecture
• Resolution limited by precision of Compare /
  Subtract / Multiply
• Comparator requirements are relaxed by two
  threshold per stage (and some error correction)

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ADC Stage



-
k Bit
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Pipeline ADC

• Shift value through many stages
• Can process one new value per cycle
• More hardware
• Faster
• Can scale cells for lower precision in later cells

Stage 1
Stage 2
Stage m-1
Stage m
Vin
Bit Alignment RSD Correction
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Voltage vs. Current

• Signal can be voltage or current
• Voltage
• Often natural quantity delivered by circuit
• Comparison simple
• Add / Subtract duplication with switched
  capacitor circuits
• Large swings
• Needs linear capacitors
• Current
• May require U-gtI conversion
• Low swing operation
• Add / Subtract very simple
• Duplication with multiple current copy add
• Can do with simple, small capacitors
• No obvious winner

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Standard Current Memory Cell

• Tracking phase Diode connected transistor
• Sample on gate capacitance
• Drawbacks
• Charge injection is signal dependent
• Low output resistance current dependent
• Input potential current dependent
• Large storage cap (low leak) decreases speed

Iin / Iout
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Pixel Layout
Two 8 Bit ADCs Current memory cells, Comparators,
Reference sources. Optimized, rad hard layout
ADC timing signals (can be shared)
110µm
2 x Output Logic(shift registers) Very
conservative layout Using standard cells
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ADC Characteristic

• 8 Bit ADC output vs. injection DAC value

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ADC Noise / INL

• Plot deviation from ideal value for various
  inputs
• Width mostly from noise in input stage

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Pipeline ADC (Design Study)

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Comparison ADC from D. Muthers, Kaiserslautern

• Voltage mode
• Cyclic Pipeline version
• Early version used in TRAP chip

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Comparison
HD, I mode Cyclic HD, I mode Pipeline KL, V mode Cyclic KL, V mode Pipeline Commercial IQ-Analog
ENOBs 8 (9) 9 (design) 9.2 _at_ fin5MHz 9.7 9
speed 6 MS/s 25 MS/s 10 MS/s 75 MS/s 80 MS/s
Power 1 mW 4.5 mW 9.5 mW 30 mW 8 mW
Layout area 3.000 µm2 (rad hard) 10.000 µm2 (rad hard) 110.000 µm2 (non rad hard) gt 200.000 µm2 (non rad hard) 210.000 µm2 (0.13µm)
Additionally Shift register Delay registers ??? ??? -
FoM pJ/conv 0.65 0.35 1.6 0.48 0.2

• FoM P / 2ENoB / f 1012 (small is good)
• ADC from HD are VERY small

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Thank you!
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Simple Serial Data Driver

• Peter Fischer, ziti, Uni Heidelberg

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Goal

• Study a serial driver suited to directly drive an
  FPGA
• Find out how
• Complex
• Large
• Power hungry
• it is.
• Later study copper transmission
• how long can we go ?
• How fast can we go ?
• For which type of cable ?
• for which power requirement ?

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Design choices

• Use (free) Aurora protocol from Xilinx
• No back channel
• No channel bonding
• Minimize protocol engine
• Use radiation hard library for a test

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Aurora Protocol

• Physical layer interface electrical levels,
  clock encoding, symbol coding
• Channel initialization and error handling
• Link layer
• Beginning / End of data
• IDLE
• Clock compensation
• 8B/10B encoding
• Arbitrary data format, Data packets with
  arbitrary length
• 4 Phases
• Initialization
• Synchronization of receiver clock (send some
  syncs)
• Data transmission
• Idle
• Must inject clock compensation characters from
  time to time

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Components

• FIFO (data buffer)
• Control FSM
• 8b/10b Encoder
• Serializer
• LVDS-Driver

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Initialisation
RESET
TXRES_0
ln_cnt lt N2
TXRES_1
zur Validierung
res_cnt lt 3
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Validation
VAL/A/
VAL/R/
von Initialisierung
idle_cnt 32
idle_cnt lt 32
idle_cnt 32
VAL/K/
val_cnt 60
val_cnt 60
val_cnt 60
CV_1
CV_0
IDLE / Daten
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Idle
ev_cnt lt 12
CC_1
ccc_cnt 10000
ccc_cnt 10000
IDLE/A/
IDLE/R/
idle_cnt 32
ccc_cnt 10000
von Daten / Valid.
idle_cnt 32
idle_cnt lt 32
IDLE/K/
valid_data even
valid_data even
valid_data even
Daten
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Data Transfer
CC_4
CC_3
SCP_0
SCP_1
von IDLE / Val.
valid_data
!valid_data !even
PADDING
DATA
CC_2_0
CC_2_1
!valid_data even
!valid_data
CC_5_1
CC_5_0
ECP_0
ECP_1
IDLE
!valid_data
valid_data
Daten
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8B/10B Kodierung

• Bei der 8B/10B Kodierung können Sequenzen von
  maximal 5 aufeinander folgenden Nullen oder
  Einsen im seriellen Datenfluss entstehen.
• Die Anzahl der Einsen pro Symbol unterscheidet
  sich maximal um zwei von der Anzahl der Nullen.
• Zwischen zwei beliebigen Punkten im seriellen
  Datenfluss können maximal 6 Einsen mehr als
  Nullen (oder umgekehrt) vorkommen
• Drei der Kontroll-Symbole, noch Kommas genannt,
  besitzen Bitmuster, die sonst bei keiner
  Kombination von 2 gültigen 10-Bit Symbolen
  vorkommen können.

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Serializer

• For simplicity Realize in CMOS
• Use shift register with load
• Load generation most time critical
• Several circuits have been compared
• Minimal speed 600 MHz
• Reached 1.9GHz with standard cells

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Test circuit on Xilinx Evaluation board

• Generate Aurora compatible parallel data stream
• Send to MGT serializer
• Loopback via SATA cable
• Receiver uses Aurora protocol

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Sample result data transfer and Idle
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Synthesis with VST library

• First Using VST library

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Simplification

• Try designs with NO clock compensation characters

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Synthesis with Rad hard library
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Power estimation

• No LVDS driver (which will dominate!)
• Using VST Library
• Rad hard x4

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Place Route

• 200 x 200mm2 for rad had design

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Next steps

• Study realistic, fast LVDS driver
• Study cable properties modelling
• First step Simulated eye-diagram with
  Kaiserslautern driver 10 cable, 24AWG (no
  pre-emphasis)

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Thank you!