Summary DAQ

1
Summary DAQ

• Walter F.J. Müller, GSI, Darmstadt
• 12th CBM Collaboration Meeting17 October 2008

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This year'sbig event
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Config September Test Beam _at_ GSI
The Plan
DABC
OnlineAnalysisROOT
discr
Basic BeamDiagnostics
FEB1nxGen
BEAMAUX...
MAPMT Tests
FEB1nxGen
MAPMT
FEB1nxGen
GEMVECC
GEM chamberTests
FEB1nxGen
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Beaming into an all new Territory

• All is new in the setup
• Detectors
• FEB (front end board)
• ROC (read out controller)
• DAQ
• Analysis
• and the whole paradigm go self-triggered and
  time-stamped
• Huge effort by many persons to MAKE FEE/DAQ WORK
• FEB R.Lalik (AGH) and C.Schmidt (GSI) build 3 FEB
  Rev B boards
• ROC N.Abel, S. Müller-Klieser (KIP), and S.Linev
  (GSI) did all levels of data handling
• DAQ-1 R,Karabowicz (GSI) setup n-XYTER test
  control
• DAQ-2 S.Linev, J.Adamcewski, V.Friese (GSI) setup
  DAQ and Online Analysis

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Config September Test Beam _at_ GSI
The real thing
DABC
ROC
Eth
FEB1nxGen Rev B
A
SYNC-M
SYNC-S
B
AUX
FEB1nxGen Rev B
OnlineAnalysisROOT
ROLU
discr
NIM toECL toLVDS
STS Test
BEAM.
discr
Basic BeamDiagnostics
GEMVECC
FEB1nxGen Rev B
GEM chamberTest
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STS
7
STS
GEM
some glue
SEU
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DAQ Test Beam Summary

• The whole chain worked
• Radek saw the very first spill in the online
  monitor !
• we had only about 7 hours beam over 3 days, and
  took data already on day one.
• 1st successful proof of concept
• everything worked 'in principle'
• Good basis to get all the details right
• sure we had some 'surprises' and 'undocumented
  features'
• can all be addressed now based on real experience

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Next Steps
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Next Steps Three Lines of Action

• Basic Laboratory Tests
• The Starter Kits
• FEE/DAQ for first round of Demonstrators
• proof of concept at module level
• do by end 2009 (STS) or early 2010 (RPC)
• Design of CBM readout chain
• towards ROB's and FLES interface

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The Starter Kits
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Config n-XYTER Starter Kit
No special infrastructure needed, just ROC PC
FEB1nxGen
OnlineAnalysisROOT
Det
I know It's overdue
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Config TDC Starter Kit
156/250 MHzclock
SYNC_TDC andSYNC_250 isgenerated in ROC
Det
FEET
OnlineAnalysisROOT
8 channel preamplifierdiscriminatortime
digitizer
No special infrastructure needed, just ROC PC
Just an adapter2 ROC user ports? 8 FEET
ports clock inputs
Planned for summer '09
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STS Demonstrator 0 In-DepthSensor Test
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Config Test Beam _at_ IHEP
April '09
BeamTelescope
Si StripDemonstrator 0
RFDUT
OnlineAnalysis
discr
FEB1nxGen
BEAMAUX...
Hybrid DAQSystem triggered time-stamped
High precisionbeam tracker(25 µm pitch)from
SVD-2experiment
MIDAS
someauxdets
SYNCmessagesender
SVD-2BeamTracker
CAMAC DAQ System
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STS RPC Demonstrator 1
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DAQ over Optics Overview

• Use one optical link for
• clock distribution
• time synchronization
• data transfer
• controls traffic
• Specific communication protocol for CBM usage
• Guarantee for Deterministic Latency Messages
  (DLM)
• High data bandwidth for data stream ROC gt ABB
• High reliability for control messages ABB gt ROC
• Fault detection and fault tolerance

FEB
ROC
FEB

ABB
DCB
FEB
ROC
FEB

FEB
ROC
FEB

ABB
DCB
FEB
ROC
FEB
DCB F. Lemke. U. Brüning, ZITI HdABB Wenxue
Gao, A. Kugel, ZITI Hd
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Data Combiner Board

• Programmable core logic
• Xilinx FPGA - Virtex-4 FX60
• Platform ROM ensures low configuration time
• High speed serial links 6x SFP connectors
• DDR2-DRAM (32bit wide, up to 512MByte)?
• FLASH memory (512MBit)?
• Gigabit-Ethernet Transceiverwith RJ45-Connector
• Programming infrastructureover JTAG and USB
• Connectors for user-specificMezzanine Boards
• Various additionalstandard interfaces

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CBM Protocol Features

• Standard initialization sequence
• Forward error correction of 1-Bit for all special
  characters
• Protocol is extendable to continue sending over
  switched and routed networks
• Open-ended hierarchical structure for
  concentrator network
• Optimized data bandwidth up to 91.428 ( 73.148
  with 8b/10b)
• Fast and efficient administration packets
• Well defined Deterministic Latency Messages
• Retransmission for Control Packets
• FPGA implementation easily portable to ASIC

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Config CBM STS Demonstrator 1
12 ROC3 DCB3 ABB some detailsyet to
befinalized ?
FEB1nxGen
BEAMAUX...
DCB backplane
CBMSTSDemo 1
DABC
CBMSTSDemo 1
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Config CBM RPC Demonstrator 1
156/250 MHzclock
156 MHz clock SYNC_TDCdistribution
SYNC_TDC andSYNC_250 isgenerated in ROC
OnlineAnalysis
CLKdist
FEET
DABC
CBMM-RPCDemo 1
FEET
FEET
FEET
FEET
FEET
Startcounter
Hybrid DAQSystem triggered time-stamped
someauxdets
SYNCmessagesender
RPCTestBench
FOPI RPCTest Environment
MBS System
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Towards the real thing
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Design of the CBM readout chain

• 'Starter Kits' and '1st round demonstrators' use
  existing or pre-prototype read-out ASIC's, prime
  objective is fast availability to support tests
  of concepts and building blocks.
• Key aspects for final CBM readout chain
• scalability to full CBM detector size and data
  rates
• provide interface to FLES (First Level Event
  Selector)
• adapt to radiation environment
• determine where COTS components can be used
• minimize functionality in exposed areas (on
  detector)
• put complex logic into unexposed or shielded
  areas

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Cave Layout
Drawing W. Niebur
For doses consult FLUKA calculations by D. Bertini
Space foelectronics andother services
Shielding
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ROCDCB ? ROB
on detector
in annex building
in 'cellar'
FLES
FEB
STS
FLES
FEET
RPC
ROC
datadigitization
dataaggregation
dataaggregation buffering
dataprocessing
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Summary

• We just got started, 'beamed in reality'
• Clear path for the level 0 and 1 demonstrators
• DAQ Workshop in December
• coordinate design work on CBM readout chain
• finalize DAQ/FLES IMoU part

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The End
Thanks for your attention