Real-Time Embedded Software Synthesis ?????????

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Real-Time Embedded Software Synthesis?????????

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What do I want to talk about ?

• What is a real-time system?
• What is an embedded system?
• Why software?
• Why synthesis?
• How to generate code automatically?
• Real-world applications?
• Future work?

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What is a REAL-TIME SYSTEM?

• Timely Response
• Predictable Response
• System Correctness
• Timing (period, deadlines, etc.)
• Function
• Constraints
• Hard (meet ALL deadlines)
• Soft (miss SOME deadlines)

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Examples of Real-Time Systems
air crafts
telecommunications
multimedia servers
automobiles
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What is an EMBEDDED SYSTEM?

• Installed in a larger system
• Dedicated task
• Small Memory Space (200400 KB)
• Low Processing Power (100200 MHz)
• Unstable Environment (mobile, )
• Reactive
• Real-Time

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Embedded Systems Example
research lab equipments
space crafts
factory automation
medical instruments
home appliances
office equipments
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Embedded System Architecture
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Why SOFTWARE?

• more than 70 software in many real-time embedded
  systems!!!
• software is more flexible and easily
  reconfigurable, hence more errors!!!
• real-time ? need correct software
• embedded ? need small, efficient software

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Why SYNTHESIS?

• More software ? high complexity ? need for
  automatic design (synthesis)
• Eliminate human and logical errors
• Relatively immature synthesis techniques for
  software
• Code optimizations
• size
• efficiency
• Automatic code generation

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How to generate CODE automatically?

• Real-Time Embedded System Model? Set of
  concurrent tasks with memory and timing
  constraints!
• How to execute in an embedded system (e.g. 1 CPU,
  100 KB Mem)? Task Scheduling!
• How to generate code?Map schedules to software
  code!
• Code optimizations?Minimize size, maximize
  efficiency!

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Design Issues and Solutions
Proposed Solutions
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Real-Time Embedded System Model
Each arc from a place is either a unique outgoing
arc or a unique incoming arc to a transition.
Time Free-Choice Petri Nets (TFCPN)
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Synthesis Algorithm (Hard RTES)

• Synthesize_Hard_RTES(S, ?, ? )
• QSS Quasi_Static_Schedule(S, ?)
• If (QSS NULL) return MemOverFlow
• RTS Real_Time_Sched(S, QSS, ? )
• If (RTS NULL) return RTS_Error else Code
  Code_Gen(S,QSS,RTS)
• return Code

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Synthesis Algorithm (Soft RTES)

• Synthesize_Soft_RTES(S, ?, ? )
• QSS Quasi_Static_Schedule(S, ?)
• If (QSS NULL) return MemOverFlow
• FIB Firing_Interv_Synth(S, QSS, ? )
• If (FIB NULL) return FIB_Error else Code
  Code_Gen(S, QSS, FIB)
• return Code

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Quasi-Static Scheduling

• TFCPN

Conflict-Free Components
MemoryOK!!!
Quasi-Static Schedules
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Real-Time Scheduling

• Single Processor
• Worst Case Timing Analysis
• Rate Monotonic (RM)
• fixed priority
• small period ? high priority
• Earliest Deadline First (EDF)
• dynamic priority
• early deadline ? high priority

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Firing Interval Bound Synthesis

• 2 issues in Soft Real-Time Embedded System
  Control
• Synchronization Wait (for completion of other
  tasks)
• Real-Time Specification (complete before
  deadlines)
• Proposed Solutions
• Postpone Release Time ? ? ? ?w, ?wgt 0
• Advance Finish Time ? ? ? ? ?n, ?ngt0

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Code Generation

• generate_code(S, QSS1, QSS2, , QSSn, RTS)
• for i 1, , n
• Di create_process(QSSi)
• for j 1, , Indep_Tasks(Ai)
• dij create_task(QSSi)
• generate_task_code(dij)
• add_task(dij, Di)
• create_main()
• output for(i0, iltlength(RTS) i)
• for k 1, , RTS output_code(Dik)
• output

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Optimal Code Hierarchy
Main Program
TFCPN
Tasks Independent Source Transitions
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Example

• S F1, F2

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Conflict Free Components for F1
Quasi-Static Scheduling
v12 (t11, t13, t15, t15) 13 ? ?(v12) ? 26
v11 (t11, t12, t11, t12, t14) 11 ? ?(v11) ? 22
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Conflict Free Components for F2
Quasi-Static Scheduling
v21 (t21, t22, 2t24, 4t26, t28, t29, t26)31
? ?(v21) ? 68
v22 (t21, t23, t25, 2t27, t28, t29, t26)15
? ?(v22) ? 36
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Real-Time Scheduling
Task Priority ?i ?max(?1) ?max(?2)
T1 1 100 26 48
T2 2 110 68 68
Schedulable Yes No
Algorithms RM, EDF
?1 v11, v12 ?2 v12, t11 t12 k ? v12 t11
t12 t14, k ? 1
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CASE STUDY AN ATM VIRTUAL PRIVATE NETWORK SERVER
WFQ SCHEDULER
CLASSIFIER
CONGESTION CONTROL (MSD)
ATM OUT (155 Mbit/s)
ATM IN (155 Mbit/s)
SUPERVISOR
DISCARDED CELLS
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ATM Server Example
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Schedule Results 49 markings 14 schedules 63
instructions 12 Kbytes Memory
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14 Schedules of MSD in ATM
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Conclusions

• Software needs to be synthesized automatically
  because it is getting more and more complex!
• Hard RTES Synthesis Method QSS RTS
  Code-Generation
• Soft RTES Synthesis Method QSS FIBS
  Code-Generation
• ATM VPN Server Example showsfeasibility of our
  approach

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Current and Future Work

• Integrate Time Memory Scheduling
• A general Petri Net system model
• Java Implementation install into embedded
  systems such as PDA for dynamic code change and
  management by user (web computing)
• C Code Generation for embedding into prototyping
  systems such as SoC design and verification
  platform