Baring It All to Software: Raw Machines

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Baring It All to SoftwareRaw Machines

• Waingold, Taylor, et. al.
• Massachusetts Institute of Technology, Lab. for
  CS
• Presented by Garver Moore for
• ECE 259 Advanced Computer Architecture II
• Prof. D.J. Sorin
• Duke University

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These three trends . . .

• Verification Complexity and Constraints
• - Superscalar verification
• - Dynamic execution structures ? Area,
  Complexity
• - Corner cases
• 2) Chip Wire Length Constraints
• - Pipelined communication b/w resources
• - Clock net limits
• - Xmission-line design
• 3) Dynamic Workload Space
• - Changing application workloads
• - Y2K ISA appropriate for Y2K workloads
• - E.G. Streaming I/D Apps (MMX / SSE)?

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. . . motivate Raw Architectures

• Philosophy Tile machine (a la 128-CMP)
• Per tile
• - Instruction Stream
• - Cache (I D and memories)
• - Functional units (vis regs, ALU)
• - Switch (reprogrammable)
• - (Re)configurable units (More on this later)
• - Leverage STATIC information
• - Provide correctness for dynamic events

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?Proposed Raw tile
3 Distinct Approaches
Raw Superscalar Multiprocessor
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Configurable Logic (CL)

• Do-it-yourself architecture extensions
• Create customized instructions
• Example Game of Life benchmark drop 22 cycle
  software sequence to 1 instruction

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Raw vs. Other Architectures I

• Systolic Arrays (Mark II Colossus)
• - slightly more recently, NuMesh (MIT)
• - Almost ZERO support for dynamic
• events, reconfiguration, patterns.
• FPGAs
• - Configurable, application specific
• VLIW
• - large Register namespace
• - Distributed register file
• - Massive compiler dependency

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Raw vs. Other Architectures II

• Multiscalar
• - Deceptive similarity
• - Resources unexposed
• - E.G. Value forwarding
• CMP
• - Simple replication
• - Message startup / synchronization
  performance issues
• IRAM
• - on-chip balance.
• - still, long bitlines and multibanked memory
  delays
• - might suffice now (1997) but in future
  processes will be exposed

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Results RawLogic

• FPGA Implementation
• Does not support general instruction processing
  converted static control sequences into state
  machines
• Less flexible, more compilation time

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Questions / Discussion I

• Small register name-space problem?
• Reducing HW support . . . opposes current
  trends, but more area and reduced verification
  complexity. Taken together, these benefits can
  make the software synthesis of complex operations
  competitive with hardware for overall application
  performance. (Emphasis mine)
• Limits of do-it-yourself ISA?
• Where is the dynamic limit? I/O? Contexts?
• Along same vein, appropriate performance
  evaluation? Or too-tailored (i.e. tarantula)
• Market size?

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Questions / Dicussions II

• How have innovations since 1997 affected this
• Is there a limit to multiple-granularity
  reconfigurabilitys usefulness?
• The Prophecy In 10 to 15 years, we believe that
  giga-xistor chips faster switch speeds, and
  growing compiler sophistication will allow a Raw
  machines performance/cost ratio to surpass that
  of traditional architectures for future,
  general-purpose workloads
• Dynamic event support too thin?
• The Google Test