ROD FDR / PRR Firmware Overview

1
ROD FDR / PRRFirmware Overview

• Introduction
• Design Overviews
• Device Utilisation
• Firmware Management
• Conclusion

2
Introduction

• Input FPGA
• Data formatting buffering
• Switch FPGA
• buffering, packet building S-link control
• Monitor FPGA
• VME-accessible RAM
• (PCI to daughter card embedded PC core)
• VME FPGA
• motherboard registers, chip selects
• VME CPLD
• DTACK, BRDSEL, Reset register System ACE
  Control

3
Input Firmware Variants

• 13 variants of Input FPGA firmware required
• different data sources compression levels
  neutral
• Compiled into 8 System ACE collections
• Only Input FPFA firmware differs between variants

4
Input FPGA Overview

• Input FPGA divided into 2 blocks
• Formatting Logic
• front-end data processing
• specific to given Input FPGA variant
• Common Logic
• back-end interface to Switch FPGA
• common to all Input FPGA variants

Input FPGA
Formatting Logic
Common Logic
5
Input FPGA - Formatting Logic

• 13 f/w variants required for
• 1 Neutral format
• 10 Native formats (without compression)
• 2 Compression formats (see next slide)
• Suppression
• Subslice suppression
• Zero suppression
• Error checking
• GLink down
• GLink protocol error
• GLink parity error
• LVDS link error
• BCN mismatch
• Maximizing data throughput
• 1 tick DAV gap for native formats
• 3 ticks DAV gap for neutral format

Control Signals
X 4
Write Enable
GLink DAV
FIFO Data
GLink Data
Error
6
Input FPGA PPM Compressed Formatting Logic
ASIC 0
ASIC 1
ASIC 2
ASIC 15

• Requires more resources than other formats
• Data arrive serially 1 ASIC / G-link pin
• Rotation, buffering (BlockRAM)
• MUX to compression algorithm 1 channel / time
• Lossless compression deviations from minimum
  value of channel
• Variable length bit fields
• Most efficient of 6 encoding schemes applied to
  channel
• Requires PPM data of 1 LUT 5 FADC slices
• Noise dominates data compression tuned for this
• Compression algorithm well tested in physics
  simulation 70 data reduction c.f. requirement
  46
• Output bit-stream chopped into as many S-link
  words as required
• No hardware testing or simulation of complete
  FPGA
• Device utilization is a concern, but optimization
  seems likely
• PPM Super-Compressed very similar architecture
  data thresholded before compression

Input data from 1 G-link 1 PPM
B
B
B
B
A
A
A
A
Buffer
Compression
bitstream
bitstream
bitstream
Common Logic
7
Input FPGA Common Logic

• Data buffering
• Event Manager FIFO stores event lengths error
  flags
• Handshake to Switch
• Generates status words for overflowed missing
  (timed-out) event packets
• Recovers from error conditions without
  intervention
• All FIFOs have programmable BUSY thresholds
• Data EvtMng FIFOs built from BlockRAM
• BCN FIFO distributed RAM
• Clock domains crossed only by asynchronous FIFOs

8
Switch FPGA

• Cascaded switch structure
• 3 Slink routing configuration
• 5 Input FPGAs
• 4 Output Slinks
• Over 100 combinations
• Complex flow control
• Synchronize 5 input FPGAs, 4 SLinks and 1 TTC
  stream
• Complicate timeout behaviour
• GLink timeout
• TTC trigger type timeout

9
Switch FPGA Slink routing mode 0
10
Switch FPGA Slink routing mode 1
11
Switch FPGA Slink routing mode 2
12
Monitor FPGA

• Receives data from Switch FPGA, copied from Spy
  buffers
• 4 x Rocket IO transceivers (total 4 Gbit/s)
  (untested)
• 20 x160 MHz point-point links (3.2 Gbit/s)
• Can process data for monitoring purposes
• 2 CPUs in FPGA (XC2VP20) external instruction
  RAMs
• PCI interface using commerical core (33 MHz, 64
  bit) to PMC daughter board (untested)
• interface to external Dual-Port RAM (64K x 32)
  with VME access (untested)
• Monitor FPGA intended to provide capacity for
  monitoring as need arises
• As yet firmware undeveloped as no clear
  requirement has been identified
• Current firmware consists only of VME interface,
  data links to Switch FPGA and interface to Dual
  Port RAM.

13
VME CPLD FPGA

• VME CPLD
• Implements key VME functions
• DTACK, BRDSEL, Reset register System ACE
  Control
• VME access to board possible if FPGAs fail to
  configure configuration can be initialised
• VME FPGA
• Generates chip select signals
• Implements motherboard Register map
• I2C interface to TTCrx
• Access to System ACE internal registers

14
Device Utilisation (1)

• VME CPLD
• - XCR3384XL
• Macrocells 114/384 30
• Pterms 148/1152 13
• Registers 48/384 13
• Pins 145/208 70
• Fn Block Inputs 161/960 17
• VME FPGA
• - XC2VP20-5ff896
• Slice Registers 242/18,560 1
• 4 input LUTs 399/18,560 2
• IOBs 266/556 47
• Block RAMs 1/88 1
• Monitor FPGA
• - XC2VP20-5ff896

• Switch
• - XC2VP30-5ff896
• Slice Registers 4,743/27,392 17
• 4 input LUTs 6,491/27,392 23
• IOBs 463/556 83
• Block RAMs 60/136 44
• Input FPGA, all except PPM compressed
• - XC2VP20-5ff896
• Slice Registers 3,0967,799/18,560 1642
• 4 input LUTs 5,0218,415/18,560 2745
• IOBs 264/556 47
• Block RAMs 64/88 72

15
Device Utilisation (2)

• Input FPGA, PPM compressed
• - XC2VP20-5ff896 current device
• Slice Registers 9,258/18,560 49
• 4 input LUTs 15,330/18,560 82
• IOBs 262/556 47
• Block RAMs 84/88 95
• Input FPGA, PPM compressed
• - XC2VP30-5ff896 footprint compatible
  alternative
• Slice Registers 9,258/27,392 33
• 4 input LUTs 15,330/27,392 55
• IOBs 262/556 47
• Block RAMs 84/136 61

16
Firmware Management

• Design Team
• James Edwards, Ian Brawn, Weiming Qian, Adam
  Davis, Dave Sankey
• Areas of responsibility with well-defined
  interfaces
• Design Tools
• FPGAdvantage HDL Designer, Modelsim, Precision
  Synthesis
• XISE ( EDK)
• Version Control
• Synchronicity used for version control, archiving
  file sharing archive _at_ RAL
• May move to CVS _at_ CERN when firmware more stable
• Each FPGA design has incremental revision number
  file name readable from VME
• Log in VHDL who, when, what
• System ACE collections have incremental revision
  numbers
• Distribution
• via web page
• Full history, log instructions for building ROD
  collections
• May place collections in EDMs when stable

17
Conclusion

• Most firmware well developed
• Confident further changes will be tweaks rather
  than major rethinks
• Except Input FPGA for PPM Compressed code,
  devices have plenty of spare capacity for logic
  changes
• Working practices in place will benefit us after
  production
• Some development of firmware still required,
  particularly PPM Compressed logic
• Test
• Reduce device utilisation
• Monitor FPGA undeveloped due to no current
  requirements
• Exists to provide spare resources which may prove
  useful later