CMOS Design Methodologies

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CMOS DesignMethodologies
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The Design Problem
Source sematech97
A growing gap between design complexity and
design productivity
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Design Methodology

• Design process traverses iteratively between
  three abstractions behavior, structure, and
  geometry
• More and more automation for each of these steps

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Design Analysis and Verification

• Accounts for largest fraction of design time
• More efficient when done at higher levels of
  abstraction - selection of correct analysis level
  can save multiple orders of magnitude in
  verification time
• Two major approaches
• Simulation
• Verification

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Digital Data treated as Analog Signal
Circuit Simulation
Both Time and Data treated as Analog
Quantities Also complicated by presence of
non-linear elements (relaxed in timing simulation)
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Circuit versus Switch-Level Simulation
Circuit
Switch
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Design analysis and simulation

• Spice - exact but time consuming
• discrete time steps
• circuit models
• timing simulation with partitioning and
  relaxation method

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Gate level simulation

• faster than switch level
• functional simulation
• VHDL description used

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Structural Description of Accumulator
Design defined as composition of register and
full-adder cells (netlist) Data represented as
0,1,Z Time discretized and progresses
with unit steps
Description language VHDL Other options
schematics, Verilog
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Behavioral Description of Accumulator
Design described as set of input-output relations,
regardless of chosen implementation Data
described at higher abstraction level (integer)
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Behavioral simulation of accumulator
Discrete time
Integer data
(Synopsys Waves display tool)
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Design verification
Electrical verification

• checking number of inversions between two C2MOS
  gates
• checking pull-up and pull down ratio in
  pseudo-NMOS gates
• checking minimum driver size to maintain rise and
  fall times
• checking charge sharing to satisfy noise-margins

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Design verification
Timing verification

• Spice too long simulation time
• RC delay estimated using Penfield-Rubinstein-Horow
  itz method
• identification of critical path (avoid false
  paths)

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Timing Verification
Critical path
Enumerates and rank orders critical timing
paths No simulation needed!
(Synopsys-Epic Pathmill)
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Design verification
Formal verification

• components described behaviorally
• circuit model obtained from component models
• resulting circuit behavior computed with design
  specifications
• no generally acceptable verifier exists

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Implementation approaches
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Custom circuit design

• labor intensive
• high time-to-market
• cost amortized over a large volume
• reuse as a library cell
• was popular in early designs
• layout editor, DRC, circuit extraction

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Layout editor
1. Polygon based (Magic) 2. Symbolic layout

• transistor symbols
• relative positioning
• compaction
• stick diagram description
• design rules automatically satisfied
• automatic pitch matching

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Custom Design Layout Editor
Magic Layout Editor (UC Berkeley)
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Symbolic Layout

• Dimensionless layout entities
• Only topology is important
• Final layout generated by compaction program

Stick diagram of inverter
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Design rule checking

• on-line DRC - rules checked and errors
  flagged during layout
• batch DRC - post design verification

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Circuit extraction
Circuit schematic derived from layout
transistors are build with proper geometry
parasitic capacitances and resistances
evaluated extraction of inductance requires 3D
analysis
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Cell-based design

• reduced cost
• reduced time
• reduced integration density
• reduced performance

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Cell-based design

• standard cell
• compiled cells
• module generators
• macrocell place and route

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Standard cell

• library contains basic logic cells - inverter,
  AND/NAND, OR/NOR, XOR/NXOR, flip-flop - AOI,
  MUX, adder, compactor, counter, decoder,
  encoder,
• fan-in and fan-out specified
• schematic uses cells from library
• layout automatically generated

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Standard cell

• cells have equal heights
• cell rows separated by routing channels

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Standard cell design
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Standard cell layout and description
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Standard cell

• large design cost amortized over a large number
  of designs
• large number of different cells with different
  fan-ins
• large fan-out for cells to be used in different
  designs
• synthesis tools made standard cell design popular
• standard cell design outperform PLA in area and
  speed
• standard cell benefit from multi level logic
  synthesis

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Compiled cell

• cell layout generated on the fly
• transistor or gate level netlist used with
  transistor size specified
• layout densities approach that of human designers

Circuit schematics with transistor sizing
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Compiled cell
Generated layout
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Automatic pitch matching
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Module generators

• logic level cells not efficient for subcircuit
  design - shifters, adders, multipliers, data
  paths, PLAs, counters, memories
• Macrocell generators - use design parameters
  like number of bits
• data path compilers - use bit slice modules
  and repeat them N times - generate
  interconnections between modules

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Datapath compilers
Feedtroughs used to improve routing
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Datapath compilers
Datapath compiler results
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Macrocell place and route

• channel routing - metal 2 horizontal
  segments - metal 1 vertical segments
• over the block routing (3-6 metal layers
  used)

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Macrocell place and route
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Array-based design implementation
To avoid slow fabrication process which takes
3-4 weeks

• mask programmable arrays
• fuse based FPGAs
• nonvolatile FPGAs
• RAM based FPGAs

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Mask programmable arrays

• gate-array - similar to standard cell
• sea-of-gate - routed over the cells (high
  density) - wires added to make logic gates
• challenge in design is to utilize the maximum
  cell capacity
• utilization lt 75 for random logic design

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Mask programmable arrays
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Macrocell Design Methodology
Macrocell
Interconnect Bus
Floorplan Defines overall topology of
design, relative placement of modules, and global
routes of busses, supplies, and clocks
Routing Channel
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Macrocell-Based DesignExample
SRAM
SRAM
Data paths
Routing Channel
Standard cells
Video-encoder chip Brodersen92
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Gate Array Sea-of-gates
Uncommited Cell
Committed Cell(4-input NOR)
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Sea-of-gate Primitive Cells
Using oxide-isolation
Using gate-isolation
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Sea-of-gates
Random Logic
Memory Subsystem
LSI Logic LEA300K (0.6 mm CMOS)
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Prewired Arrays

• Categories of prewired arrays (or
  field-programmable devices)
• Fuse-based (program-once)
• Non-volatile EPROM based
• RAM based

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Programmable Logic Devices
PAL
PLA
PROM
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Fuse-based FPGAs
Actel sea-of-gate and standard cell approach
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Fuse-based FPGAs
Example XOR gate obtained by setting A1,
B0, C0, D1, SASBIn1, S0S1In2
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Fuse-based FPGAs
Anti-fuse provides short (low resistance) when
blown out
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Nonvolatile FPGAs

• programming similar to PROM
• erasable programmable logic devices - EPLD
• electrically erasable - EEPLD
• design partitioned into macrocells
• flip-flops used to make sequential circuits
• software used to program interconnections to
  optimize use of hardware
• input specified from schematics, truth tables,
  state graphs, VHDL code

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EPLD Block Diagram
Macrocell
Primary inputs
Courtesy Altera Corp.
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RAM based (volatile) FPGAs

• programming is fast and can be repeated many
  times
• no high voltage needed
• integration density is high
• information lost when the power goes off

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XILINX FPGAs

• configurable logic blocks CLBs used
• five input two output combinational blocks
• two D flip flops are edge or level triggered
• functionality and multiplexers controlled by RAM
• RAM can be used as look-up table or a register
  file

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XILINX FPGAs
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XILINX FPGAs

• each cell connected to 4 neighbors
• routing channels provide local or global
  connections
• switching matrices(RAM controlled) are used for
  switching between channels

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XILINX FPGAs
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XILINX FPGAs (XC4025)

• 32 32 CLBs
• 25000 gates
• 422 k bites of RAM
• operates at 250 MHz
• 32 kbit adder uses 62 CLBs

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XILINX FPGAs (XC4025)
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Design synthesis
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Circuit synthesis

• derivation of the transistors schematics from
  logic functions - complementary CMOS -
  pass transistor - dynamic - DCVSL
  (differential cascode voltage switch logic)
• transistor sizing - performance modeling
  using RC equivalent circuits - layout generation
• synthesis not popular due to designers reluctance

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Logic synthesis

• state transition diagrams, FSM, schematics,
  Boolean equations, truth tables, and HDL used
• synthesis - combinational or sequential
  - multi level, PLA, or FPGA
• logic optimization for - area, speed ,
  power - technology mapping

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Logic optimization

• Expresso - two level minimization tool (UCB)
• state minimization and state encoding
• MIS - multilevel logic synthesis (UCB)

Example S (A?B) Ci Co AB ACi BCi
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Logic optimization
Multilevel implementation of adder generated by
MIS II cell library from University of
Mississippi
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Architecture synthesis

• behavioral or high level synthesis
• optimizing translation e.g. pipelining
• Cathedral and HYPER tools
• HYPER tutorial and synthesis example
  http//infopad.eecs.berkeley.edu/hyper

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Architecture synthesis example
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Architecture synthesis
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Vertical and Orthogonal CMOS COSMOS
Savas Kaya

• Stack two MOSFETs under a common gate
• Improve only hole mobility by using strained SiGe
  channel
• pMOS transconductance equal to nMOS
• Reduce parasitics due to wiring and isolating the
  sub-nets

COSMOS Complementary Orthogonal Stacked MOS
Conventional CMOS
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Technology Base

• Strained Si/SiGe layers
• Built-in strain traps more carriers and increases
  mobility
• Equalhigh electron and hole mobilities (Jung et
  al.,p.460,EDL03)
• SOI (silicon-on-Insulator) substrates
• active areas on buried oxide (BOX) layer
• Reduces unwanted DC leakage and AC parasitics

Cheng et al., p.L48, SST04
Mizuno et al., p.988, TED03
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COSMOS Structure

• Single common gate mid-gap metal or poly-SiGe
• Ultra-thin channels 2-6nm to control
  threshold/leakage
• Strained Si1-xGex for holes (x?0.3)
• Strained or relaxed Si for electrons
• Substrate SOI

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COSMOS Structure - 3D View I

• Single gate stack mid-gap metal or poly-SiGe
• Must be engineered for a symmetric threshold

In units of mm
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COSMOS Structure - 3D View II

• Conventional self-aligned contacts
• Doped S/D contacts p- (blue) or n- (red) type
• Inter-dependence between gate dimensions

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COSMOS Gate Control

• A single gate to control both channels
• High-mobility strained Si1-xGex (x?0.3) buried
  hole channel
• High Ge eliminates parallel conduction and
  improves mobility
• Lowers the threshold voltage VT
• Electrons are in a surface channel
• Requires fine tuning for symmetric operation

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3D Characteristics 40nm Device

• Symmetric operation
• No QM corrections
• Lower VT
• Features in sub-threshold operation
• Related to p-i-n parasitic diode included in 3D

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COSMOS Inverter

• No additional processing
• Just isolate COSMOS layers and establish proper
  contacts
• Significantly shorter output metallization

Top view
Peel-off top views
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3D TCAD Verification

• Inverter operation verified in 3D

40nm COSMOS NOT gate driving CL1fF load
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Applications

• Low power static CMOS
• Should outperform conventional devices in terms
  of speed
• Multiple input circuit example NOR gate
• Area tight designs
• FPGA, Sensing/testing, ?power etc. ?