Review of

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Review of Register Binding for FPGAs with
Embedded Memoryby Hassan Al Atat and Iyad Ouaiss

• Lisa Steffen
• CprE 583

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Outline

• Introduction
• Motivation
• Proposed Memory Binding Technique
• Results
• Strengths and Shortcomings
• Conclusion

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Introduction

• Early FPGAs
• Trend was to use as many logic cells as possible
• External memory banks were typically attached to
  the FPGA to hold data structures
• Communication with external memory banks very
  slow
• Motivating need for embedded memory in FPGAs
• Many register binding techniques were developed
  to minimize storage requirements of designs

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Introduction (cont.)

• Register Binding
• Aim is to minimize the number of registers
  necessary to hold all of the designs variables
• Registers are shared by multiple variables whos
  lifetimes do not overlap
• Variable lifetime is time between when the
  variable is first written to and the last time it
  is read
• Result is decreased number of required registers

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Motivation

• Current trend in FPGAs is to include large
  amounts of embedded memory banks
• Summary of Altera and Xilinx device families
  shows this trend
• Trend shows increase in logic cells and memory
  bits
• Ratio of embedded memory bits to logic cells
  sharply increasing
• Altera devices have increased from 8 to 88
• Xilinx devices have increased from 5 to 82

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Motivation (cont.)

• Research in the area of using memory blocks for
  variable storage in ASICs
• Techniques that implement register binding and
  the registers are then grouped into memory pads
• Techniques which map all variables to one memory
  and then the memory is partitioned
• Techniques that group variables into memory
  models and then binds them into registers

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Motivation (cont.)

• When targeting an ASIC, one goal when mapping
  variables to memories is minimizing the number of
  memories used
• FGPAs have a fixed number of embedded memories,
  minimizing the number used is not necessarily a
  goal
• Interconnection overhead may be improved by using
  more memories
• Motivates need for an FPGA memory binding
  technique

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Memory Binding

• Registers are traditionally implemented using
  logic resources
• Results in decreased utilization from placement
  and routing congestion
• Logic utilization can be improved by making use
  of the available memory blocks through the use of
  memory binding

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Memory Binding

• Register binding maps variables to registers
  based on their lifetimes
• Memory binding maps variables to memories based
  on their read access times and write access times
• Variables may be mapped to the same memory if
  they do not conflict
• Variables conflict if they are read in the same
  time step or if they are written to in the same
  time step

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Memory Binding

• The Algorithm
• A list is obtained of every variable in the
  design
• Two lists maintained for every memory bank used
  for memory binding
• beginList contains all of the writing times for
  all of the variables mapped to the memory bank
• endList contains all of the read times for all of
  the variables mapped to the memory bank

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Memory Binding

• The Algorithm (cont.)
• Any unassigned memory whos write time(s) are not
  found in the beginList and whos read time(s) are
  not found in the endList are added to the memory,
  read/write times are added to the appropriate
  list
• Continue until all variables are mapped

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Results

• Performance of Memory Binding technique was shown
  by applying the technique to three benchmark
  synthesis results
• Number of logic cells used with no variable
  binding techniques were compared with the number
  of logic cells used with the memory binding
  technique as well as with two register binging
  techniques Clique Partitioning and Left-Edge
  Algorithm

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Results

• All three techniques reduce the total number of
  logic cells occupied in the device
• Improvement by the Clique Partitioning was
  marginally better than the Left-Edge Algorithm
• Improvement by the Memory Binding technique was
  clearly greatest of the three techniques

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Resluts

• Memory Binding improvement over Clique
  Partitioning was 6 with a small resource bag
  and 40 with a large resource bag
• Memory Binding improvement over the Left-Edge
  Algorithm was 6 with a small resource bag and
  50 with a large resource bag

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Strengths

• Memory Binding makes use of the memory blocks
  which are on the FPGA
• Memory Binding results in clear area utilization
  improvements over other available variable
  mapping techniques

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Shortcomings

• Memory Binding introduces a lot of complexity
  into the design
• Memory Binding introduces three new sources of
  delay
• Variables bound to memories rather than registers
  are at a greater distance from their operators
• Memories have a larger access delay than
  registers
• Time is needed to calculate the addresses of the
  variables in memory

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Shortcomings

• The algorithm must have memory blocks available
  which can be utilized for memory binding
• Many FPGA designs are data-oriented, many designs
  may use the majority of the memory for data
  storage
• Performance was only studied in the area of logic
  cell utilization, no timing results shown from
  applying the three techniques

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Conclusion

• For specific designs, the proposed technique
  could provide many benefits
• Designs which utilize a large number of logic
  cells, but little embedded memory
• Designs which are able to utilize the memory
  binding without effecting the timing requirements
  of the design

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Conclusion

• Number of logic elements in an FPGA are also
  fixed, as the number of memory blocks are fixed
• If the design fits into the number of logic
  elements available, the cost incurred by applying
  the memory binding would be greater than any
  benefit received

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Conclusion

• Much more analysis needs to be performed with
  regards to the timing of the design after
  performing memory binding
• Most designs would not be able to incur the extra
  delay of having to access all variables from
  memory