Digital Logic

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Digital Logic

• Electricity, Gates, Components

2
Digital Logic Reading Appendix
c through C.3

• The Student shall be able to
• Define voltage, current, resistance, volts, amps,
  ohms.
• Recite ohms law
• Draw the symbol for AND, OR, XOR, NAND, NOR, NOT.
• Write mathematical statements using AND, OR, XOR,
  NOT.
• Prepare a truth table.
• Prepare a truth table for AND, OR, XOR, NOT.
• Design a circuit using Sum of Products.
• Design an efficient solution using a Karnaugh Map
  or K-Map.
• Define decoder, multiplexor, parity, adder, and
  recognize their circuit diagrams.
• Design a circuit with Logic Circuit

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Electricity
Voltage Depth Current Speed Resistance Work
or Obstructions
voltage
current
resistance
4
Resistance measured in Ohms ?
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Electricity Notation

• Voltage gt Volts V
• Current gt Amperes Amps A
• Resistance gt Ohms ?

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Ohms Law VIR

• Voltage Current Resistance (VIR)
• Resistance Voltage/Current (RV/I)

• Example
• Given
• Voltage 10 V
• Resistance 1k ?
• What is Current?
• Current I V/R
• 10/1000
• 1/100 0.01 A
• 10 mAmps

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Electronic BreadboarD
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A Digital Logic Chip

• Notch Direction
• VCC Power
• GND Ground
• 4 NAND Gates
• DIP Package

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OR, AND, NOT
 
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AND Example 1 0 0
? Truth Table 0 1
0 0 0
1 0 1
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OR Example 1 0 1
Truth Table 0 1
0 0 1
1 1 1
Clock Alternates 1 - 0
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XORExample 1 XOR 0 1
XOR Truth Table 0 1
0 0 1
1 1 0
Clock Alternates 1 - 0
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Additional Electronic Gates
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LED Display
Top Bottom Left Top Right Top Left Bottom
Right Middle Bottom Period
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Building Digital COmponents

• Multiplexor
• Adder
• Decoder

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Multiplexer - DemultiplexEr
Multiplexer
Demultiplexer
selector
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Multiplexer Selects One Input
A
Out
B
How is the solution provided mathematically?
S
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Multiplexer Selects One Input
A
Out
B
Out (A ? !S) (B ? S)
S
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Half Adder

• A, B Input bits
• S Sum
• S A XOR B
• C Carry
• C A B
• Notice there is no Carry-in

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Full Adder
Inputs Inputs Inputs Outputs Outputs
A B Cin Cout S
0 0 0 0 0
1 0 0 0 1
0 1 0 0 1
1 1 0 1 0
0 0 1 0 1
1 0 1 1 0
0 1 1 1 0
1 1 1 1 1
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Full Adder
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Encoder - Decoder
Encoder
Decoder
Output
Input
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Decoder
Input Input Input Output Output Output Output Output Output Output Output
0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 1 0 0 0 0 0 0 1 0 0
0 1 1 0 0 0 0 1 0 0 0
1 0 0 0 0 0 1 0 0 0 0
1 0 1 0 0 1 0 0 0 0 0
1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 0 0 0 0 0 0 0
Decoder
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Decoder Sums of Product Solution
Input Input Input Output Output Output Output Output Output Output Output
0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 1 0 0 0 0 0 0 1 0 0
0 1 1 0 0 0 0 1 0 0 0
1 0 0 0 0 0 1 0 0 0 0
1 0 1 0 0 1 0 0 0 0 0
1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 0 0 0 0 0 0 0
 
2 1 0 7 6 5
4 3 2 1 0
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Designing A Circuit

• Example Parity

• Define the Truth Table
• Write Sum of Products
• Optimize
• Develop circuit

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Parity

• Used in Data Communications, RAID disk systems
• Even Parity Example Each Byte sums to even
  number of 1-bits
• 0000000 -gt 0
• 1111111 -gt 1
• 0101010 -gt 1
• 1000001-gt ?
• Odd Parity Example Each 3 bits sums to odd
  number of 1-bits
• 00-gt 1
• 10 -gt 0
• 11-gt ?
• Enables ERROR CHECKING, Sometimes ERROR
  CORRECTION

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Step 1 Provide Truth TableEven Parity Output
Assures even 1 digits
Input1 Input2 Input3 Output
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
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Step 2 Write Sum of Products

•  

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Step 3 optimize

• Laws

• Boolean Algebra

• Commutative Law
• AB BA
• AB BA
• Associative Law
• A(BC)(AB)C
• A(BC) (AB)C
• Distributive Law
• A(BC) AB AC

•  

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Step 4 Develop Circuit Logic Circuit
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Traffic Light

• Green 01
• Yellow 10
• Red 00
• Succession
• Green 01 -gt Yellow 10
• Yellow 10 -gt Red 00
• Red 00 -gt Green 01

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Traffic Light Design

• Step 2
• Write Sum of Products

• Step 1
• Provide Truth Table

•  

IN0 IN1 OUT0 OUT1
0 0 0 1
0 1 1 0
1 0 0 0
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Optimization Karnaugh Maps (K-Maps)

• An Optimization Technique

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Traffic Light Design

• Step 2
• Develop K-Map

• Step 1
• Provide Truth Table

Out0
0 1
0 0
IN0 IN1 OUT0 OUT1
0 0 0 1
0 1 1 0
1 0 0 0
Out1
1 0
0 0
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Comparison Truth Table vs. K-Map

• Truth Table

• Karnaugh Map

•  

• Left columns Input
• Right columns Output

IN0 IN1 OUT0 OUT1
0 0 0 1
0 1 1 0
1 0 0 0
Out0
0 1
0 0
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Solving a K-map with 4 inputs

•  

CD
0 0 1 1
1 1 1 1
AB 1 1 1 1
0 1 0 0
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Even Parity Output Assures even 1
digitsConvert to K-Map
Input1 Input2 Input3 Output
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1

0 1
1 0
0 1
1 0
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Even Parity Output Assures even 1
digitsAnalyze K-Map

•  

0 1
1 0
0 1
1 0
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Optimized Parity ImplementationOptimized 6
Gates Original 8 Gates
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Conclusion

• Definitions

• Designing Logic

• Electricity V I R
• Symbols AND, OR, NOR, XOR, NAND, NOR
• Equation Form
• Gate Form
• Components Multiplexer, Decoder, Parity, Adder

• Define Truth Table
• Analyze
• Write Sum of Products
• Use Karnaugh Map
• Optimize in other ways
• Develop Circuit