AMICSA 2006

1
AMICSA 2006 summary
2
AMICSA 2006 in numbers

• 48 participants
• From 12 countries GR, FR, UK, NE, GE, IT, BE,
  USA, SWI, SWE, AU
• From 26 different institutions/companies
  DUTH/Space Research Lab, A2S, EADS Astrium, E2V
  (ex Atmel Grenoble), ESA, CNES, National
  Semiconductor, TRAD, Aurelia, NTUA,
  STMicroelectronics, SODERN, SRON, Fraunhofer Inst
  IC, IHP, IMST, NISR, TESAT, ETH, SUPAERO, Saab,
  IMEC, AAS, Austria Space Research Inst,
  Nucletudes, ISD.
• 17 presentations in 2 days, plenty of
  discussions, questions and answers

3
AMICSA - Applications

• CMOS Image sensors
• Video processing chain
• ADC/DAC/HSSL high speed low power telecom
  processors (mobile broadband)
• CAN transceivers
• TM acquisition data handling IO control
• Magnetometer front end
• Slow sampling high resolution

4
AMICSA Technology (I/II)

• PROCESSES
• CMOS
• Bipolar
• BiCMOS
• Si / SiGe
• bulk /epi / SOI

• FOUNDRIES
• AMS (Austria)
• AMIS (Belgium)
• STMicroelectronics (France)
• IHP (Germany)
• Infineon (Germany)
• XFab (UK)
• UMC (Taiwan)

5
AMICSA Technology (II/II)

• EDA tools, HDL DK
• Tanner
• Cadence
• Calibre (Mentor)
• Pspice / Hspice
• ADMS (Mentor)
• VHDL-AMS / Verilog-A
• Astrium UK ADC simulator

• MPW programmes
• Europractice
• CMP
• MOSIS
• vendor specific

6
AMICSA Radiation effects

• Mitigation Techniques
• (technology and function dependent)
• enclosed/bigger transistors
• guardband rings / STI / LOCOS
• avoid diffusion resistors in favor of oxide R
• epi layer / hetero-epi
• buried-layers
• low gain artificially provoked parasitic
  transistors
• DRC isolation rules
• SOI
• thinner gate oxide
• hardened libraries (re-size, cell-topology)
• ADC offset auto-zeroing (analog and digital
  correction)
• architecture hardening (open vs closed loop)
• redundancy and voting/comparing

• Rad Threats
• (TID, SEE)
• leakage currents
• Vth shifts
• parasitic transistors/ latch up
• gate rupture
• data corruption (bit flips)
• transient pulses

7
AMICSA Future Challenges

• Easier selection of process, foundry, design kit
  tools, rad mitigation techniques, quality level
• Lower cost access to design kits, manufacturing
  services
• Simulation tools. Characterising COTS (NPR,etc)
• Supporting EU foundries in low volume market
• Coordinating/reusing EU resources (e.g. rad
  tests, new libs/DK IPs), preserving industry
  competition and individual commercial interests
• Finding more resources for more tech/components
  evaluation and qualification. Sharing results !
• Maintaining good (better) communication channels
  (ESCC Working Groups , AMICSA 2008 ?,
  Harmonisation/Tech Dossiers)

8
AMICSA THANKS !

• to all participants
• to sponsors DUTH / ESA / National Semiconductor
• to organizers
• Boris Glass and ESA Conference Bureau
• Professor Emmanuel Sarris and DUTH / Space
  research Lab team !!