Pixels at MTest Presentation

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Pixels at MTest Presentation
Ryan Rivera Marcos Turqueti Detector
Instrumentation Electronic Systems
Engineering Computing Division
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ESE EXPERIENCE ON TEST BEAMS

• Working on pixels test beams since 1998.
  (First testbeam run in 1999 testing fpix0)
• Designed the whole electronic DAQ for all
  BTeV and the last two CMS test beam runs.
• Designed the pixel planes for all BTeV and
  the last two CMS test beam runs.
• Designed test stand for calibrating the
  telescope (softwarehardware).
• Participated on the development of the DAQ
  software.
• Supported all BTeV and the last two CMS test
  beam runs.

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TESTED CHIPS

• Most of the times the detector under test is
  irradiated before going to the test beam.
• Single Chips
• FPIX 0, PFIX 1, FPIX 2, PSI V1, PSI V2
• Modules
• FPIX 1 (5x1), FPIX 2 (4x1), PSI V2 (4x2), PSI
  V2 (5x2)
• Observation the output of FPIX series is
  digital while PSI series is analog, completely
  different outputs but the flexible architecture
  was able to adapt!
• We are one of few groups that have experience
  with FPIX2.1

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TESTED CHIPS
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WHAT IS AT M-TEST NOW?

• Telescope of 6 BTeV pixel detectors (50 ?m ? 400
  ?m) (legacy setup)
• 2 Y-measurement planes Y-resolution
  6.24 ?m
• 4 X-measurement planes X-resolution
  4.75 ?m
• CMS pixel detector in the center (100 ?m ? 150
  ?m)
• Triggers to CMS detector are provided by two
  upstream scintillators

CMS Pixel Document 1216-v2
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WHAT IS AT M-TEST NOW?
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WHAT ILC COMMUNITY IS LOOKING FOR IN A TEST BEAM
TELESCOPE?
ILC Detector Test Beam Workshop ILC Detector Test Beam Workshop
17-19 January 2007
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SOME REQUIREMENTS
Approximately 10 different technologies under
study for ILC vertex detector. Sensitive window
varies from single bunch (ie. lt300ns), through
50us (20 time slices per train) to integration
over the entire bunch train (1ms).
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WHAT WE READ FROM THIS?

• A friendly interface is needed for the silicon
  telescope both for software and hardware. This is
  fundamental in order to provide efficient
  integration with the chip under test.
• The DAQ must be able to deal with a good data
  rate (15MB/s).
• Support is fundamental for both software and
  hardware.
• The system must be able to be integrated with
  other detectors.
• It is very continently if the test stand and the
  test beam use the same platform.

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BASIC ARCHITECTURE
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BASIC ARCHITECTURE
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FLEXIBILITY
FERMILAB NETWORK
FIREWALL
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FLEXIBILITY
TRACKING STATIONS
OTHER IP PERIPHERICAL DEVICES
TELESCOPE ROOM
FERMILAB NETWORK
FIREWALL
TO/FROM OTHER DETECTORS ON THE BEAM LINE
MASS STORAGE
DATA ANALYSIS DAQ CONTROL ONLINE
MONITORING
DAQ SERVER WEB SERVER
CONTROL ROOM
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DATAFLOW
STATION
SERVER
ROUTER
DAQ SOFT
UDP
IPv 4
IPv 4
ETHERNET
ETHERNET
TWISTED PAIR
TWISTED PAIR
FIRMWARE
COMMUNICATION PROTOCOLS
SOFTWARE
HARDWARE
HARDWARE
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STATIONS
DETECTOR
THERMOELECTRIC COOLER
THERMOELECTRIC COOLER
LOW VOLTAGE REGULATION
HIGH VOLTAGE MODULE
POWER
ETHERNET
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STATIONS
NETWORK
MEMORY MANAGER
SECONDARY COMMANDS
TASKS MANAGER
EXTERNAL SIGNALS
FIRMWARE
TIMING
CACHE
DATA MANAGER
PRIMARY COMMANDS
ETHERNET
THERMOELECTRIC COOLING
LOW VOLTAGE REGULATION
RAM 64Mx64
Central Processing Unit (FPGA)
HIGH VOLTAGE GENERATION
ADC
DETECTOR
External Signals Trigger, Clock, Reset
PRIMARY SYSTEM
SECONDARY SYSTEM
OPTIONAL
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CAPABILITIES
A)
SYSTEM CAPABLE TO DEAL WITH UP TO 100Mbytes/s
337ns
0.95ms
30s
B)
10us
4s
C)
1us
10ms
D)
10ns
10ms
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SYSTEM TOP VIEW
TELESCOPE

• TELESCOPE BACKBONE
• DAQ Software, Hardware and Firmware
• Pixel Stations
• Slow Controls
• Mechanical support and cooling

Integration Signals
SUPPORT
USER

CALIBRATION SOFTWARE

DATABASE

ANALYSIS SOFTWARE
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UPGRADE

• What is needed (from ESE) for this upgrade?
• Software review and adapt the uffizi/pomone
  DAQ software.
• Hardware design the pixel stations network
  electronics attached to the pixel plane.
• - We already have a card (PMIC) that proves the
  concepts for HV and LV as we have the PTA2 that
  is being used currently on the FPIX2 testand.
• Firmware - write the new DAQ firmware on the
  pixel planes.

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THE DAQ SOFTWARE
Current Test Beam Software
Lorenzo Uplegger et Al
PInGA FPix2.1 Calibration Software
Marcos Turqueti, Lorenzo Uplegger, Ryan Rivera
DInA Future ILC Test Beam DAQ Software
Ryan Rivera
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THE DAQ SOFTWARE
PINGA UFFIZI
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THE DAQ SOFTWARE
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THE DAQ SOFTWARE
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WHAT DO WE HAVE RIGHT NOW?

• First version of the board with the DAQ front end
  will arrive this week.
• The board will serve as a test stand platform for
  testing the VIP chip.
• Carrier board for the VIP also provided.
• HV and low voltage system already tested, FPGA
  already tested (PTA platform).

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THE FIRST PROTOTYPE
DAQ BOARD
CARRIER BOARD