Probabilistic Soft Error Rate Estimation from Statistical SEU Parameters

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Probabilistic Soft Error Rate Estimation from
Statistical SEU Parameters Fan Wang Vishwani
D. Agrawal
Department of Electrical and Computer
Engineering Auburn University, AL 36849
USA Presently with Juniper Networks, Sunnyvale,
CA
17 th IEEE North Atlantic Test Workshop
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Outline

• Background
• Problem Statement
• Analysis
• Results and Discussion
• Conclusion

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Motivation for This Work

• With the continuous downscaling of CMOS
  technologies, the device reliability has become a
  major bottleneck.
• Sensitivity of electronic systems can potentially
  become a major cause of soft (non-permanent)
  failures.
• There is no comprehensive work that considers all
  factors that influence soft error rate.

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Strike Changes State of a Single Bit
a-particle or high-energy neutron
Logic or Memory Device
0
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Definition from NASA Thesaurus Single Event
Upset (SEU) Radiation-induced errors in
microelectronic circuits caused when charged
particles also, high energy particles (usually
from the radiation belts or from cosmic rays)
lose energy by ionizing the medium through which
they pass, leaving behind a wake of electron-hole
pairs.
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Impact of Neutron Strike on a Silicon Transistor
neutron strike
Strikes release electron hole pairs that can be
absorbed by source drain to alter the state of
the device


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Transistor Device

• Neutron is a major cause of electronic failures
  at ground level.
• Another source of upsets alpha particles from
  impurities in packaging materials.

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Cosmic Rays
Source Ziegler et al.

• Neutron flux is dependent on altitude,
  longitude, solar activity etc.

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Problem Statement

• Given background environment data
• Neutron flux
• Background energy (LET) distribution
• These two factors are location-dependent.
• Given circuit characteristics
• Technology
• Circuit netlist
• Circuit node sensitive region data
• These three factors are circuit-dependent.
• Estimate soft error rate in standard FIT units.
• Linear Energy Transfer (LET) is a measure of the
  energy transferred to the device per unit length
  as an ionizing particle travels through material.
  Unit MeV-cm2/mg.
• Failures In Time (FIT) Number of failures per
  109 device hours

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Measured Environmental Data

• Typical ground-level neutron flux 56.5cm-2s-1.
• J. F. Ziegler, Terrestrial cosmic rays, IBM
  Journal of Research and Development, vol. 40, no.
  1, pp. 19.39, 1996.
• Particle energy distribution at ground-level
• For both 0.5µm and 0.35µm CMOS technology
  at ground level, the largest population has an
  LET of 20 MeV-cm2/mg or less. Particles with
  energy greater than 30 MeV-cm2/mg are exceedingly
  rare.
• K. J. Hass and J. W. Ambles, Single Event
  Transients in Deep Submicron CMOS, Proc. 42nd
  Midwest Symposium on Circuits and Systems, vol.
  1, 1999.

Probability density
0 15 30
Linear energy transfer (LET), MeV-cm2/mg
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Proposed Soft Error Model
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Pulse Widths Probability Density Propagation
fX(x)
Delay tp
fY(y)

• We use a 3-interval piecewise linear
  propagation model
• Non-propagation, if Din tp.
• Propagation with attenuation, iftp lt Din lt 2tp.
  
• Propagation with no attenuation, if Din ? 2tp.
• Where
• Din input pulse width
• Dout output pulse width
• tp gate input output delay

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Validating Propagation Model Using HSPICE
Simulation

• Simulation of a CMOS inverter in TSMC035
  technology with load capacitance 10fF

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• Pulse Width Density Propagation Through a CMOS
  Inverter

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Soft Error Occurrence Rate Calculation for
Generic Gate
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Comparing Methods of Analysis
Factors Considered LET Spec. ReconvFanout Sens. region Occurance rate Vectors ? Altitude Ckt Tech. SET degrad
Our work Yes No Yes Yes No Yes Yes Yes
Rao et at. 1 Yes No No No Yes Yes Yes Yes
Rajaraman et al. 2 No No No No Yes No No Yes
Asadi-Tahoori 3 No No No Yes No No No No
Zhang-Shanbhag4 Yes No Yes Yes Yes Yes Yes No
Rejimon-Bhanja 5 No No No Yes Yes No No No
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Experimental Result Comparison
Ckt PI PO Gates Our approach Our approach Rao et al. 1 Rao et al. 1 Rajaraman et al2 Rajaraman et al2
Ckt PI PO Gates CPU s FIT CPU s FIT CPU min Error Prob.
C432 36 7 160 0.04 1.18x103 lt0.01 1.75x10-5 108 0.0725
C499 41 32 202 0.14 1.41x103 0.01 6.26x10-5 216 0.0041
C880 60 26 383 0.08 3.86x103 0.01 6.07x10-5 102 0.0188
C1908 33 25 880 1.14 1.63x104 0.01 7.50x10-5 1073 0.0011
Computing Platform Computing Platform Computing Platform Computing Platform Sun Fire 280R Sun Fire 280R Pentium 2.4 GHz Pentium 2.4 GHz Sun Fire v210 Sun Fire v210
Circuit Technology Circuit Technology Circuit Technology Circuit Technology TSMC035 TSMC035 Std. 0.13 µm Std. 0.13 µm 70nm BPTM 70nm BPTM
Altitude Altitude Altitude Altitude Ground Ground Ground Ground N/A N/A
BPTM Berkley Predictive Technology Model
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More Result Comparison
Measured Data Measured Data Logic Circuit SER Estimation Ground Level Logic Circuit SER Estimation Ground Level
Devices SER (FIT/Mbit) Our Work Rao et al. 1
0.13µ SRAMs6 10,000 to 100,000 1,000 to 10,000 1x10-5 to 8x10-5
SRAMs, 0.25µ and below 7 10,000 to 100,000 1,000 to 10,000 1x10-5 to 8x10-5
1 Gbit memory in 0.25µ 8 4,200 1,000 to 10,000 1x10-5 to 8x10-5
The altitude is not mentioned for these data.
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Discussion

• We take the energy of neutron to be the key
  factor to induce SEU. In real cases, there can
  also be secondary particles generated through
  interaction with neutrons.
• Estimating sensitive regions in silicon is a hard
  task. Also, the polarity of SET should be taken
  into account.
• Because on the earth surface, typical error rates
  are very small, their measurement is time
  consuming and can produce large discrepancy. This
  motivates the use of analytical methods.
• For example, a circuit may experience 1
  SEU in 6 months (4320 hours), equals 231,480 FIT.
  It is also likely that the circuit has 0 SEU in
  these 6 months, so the measured SER is 0 FIT.

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Discussion Continued

• Fan-out stems should be considered. Two
  situations can arise
• When an SET goes through a large fan-out, the
  large load capacitance can eliminate the SET, or
• If it is not canceled by the fan-out node, it
  will go through multiple fan-out paths to
  increase the SER.
• It is highly recommended to have more field tests
  for logic circuits.
• None of these SER approaches consider the process
  variation effects on SER.
• Without consideration of electrical masking, SER
  will be overestimated by 138 for a small 5-stage
  circuit Wang et al., VLSID07
• Intra-die threshold voltage variation can result
  in a peak to peak SER variation of 41 in a small
  circuit Ramakrishnan et al., ISQED07

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Conclusion

• SER in logic and memory chips will continue to
  increase as devices become more sensitive to soft
  errors at sea level.
• By modeling the soft errors by two parameters,
  the occurrence rate and single event transient
  pulse width density, we are able to effectively
  account for the electrical masking of circuit.
• Our approach considers more factors and thus
  gives more realistic soft error rate estimation.

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References

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Thank You . . .