Smart EQ

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Smart EQ

• Digital Stereo Equalizer

Dustin Demontigny David Bull
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Project Motivation

• Optimize an audio signal for a specific
  individual
• Improve on existing analog equalizer systems
• Apply DSP techniques using VHDL

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Design Goals

• Develop 10 band stereo equalizer
• User interface and control
• Minimize FPGA resources of filter
• High level of resolution (20 bit audio samples)

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Audio Interface

• Combines the XStend and XSA-100 boards
• FPGA controls the AKM sigma delta codec on XStend
  board

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VHDL Modules

• User interface selects equalizer settings
• ROM on arithmetic unit holds taps
• Handshaking between sections
• EQ interfaces to codec and provides filtering

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User Interface

• Push buttons toggle between preset values
• Preset number displayed on LED
• Gain value decoded from preset value
• Simple but very small (only 3 of FPGA)

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Arithmetic Unit

• Receives gain value and determines the filter
  coefficients
• Retrieves filter taps from ROM
• Reduces total taps by a factor of the bands (in
  our case 10)

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Equalizer

• 10 bandpass FIR digital filters
• Easy to Implement
• No stability issues
• Linear Phase Can add coefficients for each
  filter to obtain one filter that performs like
  all the individual filters

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Equalizer
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Equalizer
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Useful Applications

• Hearing aids
• Consumer audio
• Musical instrument amplifiers
• Computer soundcards

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Upgrades Enhancements

• Real-time automatic mode select
• Calibration mode
• More enhanced user interface
• Graphic display of audio spectrum (input and
  output) on VGA monitor or LCD

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Questions