Multicore Software

1
Multicore Software An overview Sandip Matte,
Netlogic
2
Agenda

• Multicore SoC
• Why Multicore ?
• Multicore Software
• Different Models
• Architecture
• Programming Challenges
• Debuggers, profileres, Optimizations

3
Multicore SoC
4
Multi-threading

• Increase CPU Performance by modest increase in
  size, power and complexity
• Based on hiding memory and IO latencies
• Very Effective with memory /IO bound applications
• Replicate minimal pipeline logic and registers
  for each additional thread to save on size,
  complexity and power

5
Need for Multicore

• CPU Technological advancements seek improved
  performance with reduced power. This is acheived
  by
• Increasing CPU frequency OR
• Adding more cores
• Issues with Increasing CPU frequency
• Technological limitations in increasing frequency
  forever
• Diminished gains from CPU frequency scaling
• Power increases linearly with frequency but not
  performance
• Reducing frequency and adding additional core
  improves performance without major increase in
  power

6
Need for Multicore

• Multicore improves multitasking and reliability
• Dedicate cores for specific functions
• e.g. Run Control and Dataplane applications on
  different CPUs
• Isolate different run-time environments on
  different core through soft and hard
  virtualization
• Adaptive Performance scaling
• Dynamically add more CPUs based on increased
  workload

7
Programming Models

CPU 3
CPU 0


CPU 1

CPU 2

• SMP all CPUs running same image and pickup
  tasks from run queue

Linux / FreeBS/Vxworks SMP

CPU 3
CPU 0

• AMP CPUs running different or same images .
  Can accomodate pipeline architecture

CPU 1

CPU 2
IPSEC on baremetal
Linux / FreeBS/Vxworks SMP
Firewall on baremetal
8
Multicore Architecture

• Resource Management
• Ownership of different resources
  (memory/peripherals etc) between CPUs
• Virtualization of resources
• Starting CPUs with different images and stopping
  them
• Shared memory allocation
• Pipeline vs SMP model
• SMP and AMP combination

9
Multicore Programming Challenges

• Avoiding race conditions
• other CPUs are free to modify memory. Shutting
  off interrupts won't help
• Using spinlocks instead of semaphores?
• spin for a few cycles instead of the semaphore
  overhead
• Using shared code segment (if possible)
• Avoid cache thrashing
• Avoiding giant locks for shared resources
• Use per-CPU data structures

10
Multicore debugging

• Debugging and Profiling complexity become
  manifold compared to single CPU debugging and
  profiling
• Debuggers Requirements - multi-core debugging
  capabilities
• Ability to stop all or a select set of CPUs
• Ability to set breakpoints on a set of CPUs while
  others are running and debug
• Ability to dump system information (not just
  per-CPU dump)

11
Multicore profilers

• Profilers Requirements
• System Wide statistics
• Ability to consolidate individual CPU / cache
  statistics (synchronize across shared memory etc)
• Ability to provide system level information to
  debug performance issues due to multi-core
  unfriendly code

12
Multicore Optimizations

• Data structures should be designed with caching
  in mind
• Flow binding to cpu is beneficial
• Avoid pipelining from one cpu to another
• Memcpy, memset, memcmp of short data can to
  converted to assignment or relational operations
• Perform only data path optimizations at the cost
  of code readability
• Use async operations wherever possible

13
Multicore software

• Questions???