Wafer Edge Exclusion

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Wafer Edge Exclusion

• Kevin Fisher

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Outline

• What is Edge Exclusion?
• Motivation for reducing edge exclusion
• ITRS Roadmap
• Problems on the Edge
• Example Copper Deposition

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What is Edge Exclusion?

• Edge of wafer considered unusable for a variety
  of reasons
• Chips entirely on wafer but too close to edge are
  still invalidated

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Yield Loss on the Edge

• Current edge exclusion is 3mm
• Reduces usable area of wafer by 2
• 300mm wafer 70685 mm2 total area
• 297mm usable area 69279 mm2
• Area loss 1406 mm2
• Athlon 64 die size 144 mm2

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Increasing Yield

• 300mm Pentium 4 Processor wafer (130nm)

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ITRS on Edge Exclusion

• Two references in 2003 Yield Enhancement report

Wafer Type 2003 2004 2005-12
Patterned 2mm 1mm 1mm
Unpatterned 3mm 2mm 2mm
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Problems on the Edge

• Chips, cracks, identification notches
• Slurry/photoresist residue
• Cleaning contaminants
• Peeling films

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Copper Interconnects

• Two problems affect edges of wafers with copper
  metal layers
• Barrier, seed layer residue
• Copper islands

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Barrier/Seed Residue
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Copper Islands
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One Solution Wet Processing Chambers

• Apply film in liquid-filled chamber
• Chemical breaks films surface tension