Reconfigurable and Evolvable Hardware Fabric

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Reconfigurable and Evolvable Hardware Fabric
Chris Papachristou, Frank Wolff
Robert Ewing Electrical Engineering Computer
Science AFRL/AFTA,
Bldg 620 Case Western Reserve
University
Wright Patterson Cleveland, Ohio 44106

WPAFB, OH 45433 September 7, 2005
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Project Overview
A novel reconfigurable processor for high
data rate agile communications Features -
Reconfigurability adaptability, - Low power,
system-on-chip technology, - Real time, robust
performance, - Fault tolerance, -
Self-healing. Platform autonomous sensor or
unit being a typical node in
space
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Concept The Big Picture
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Reconfigurability
Ability of a device to change its internal
structure, functionality, and behavior, either on
command, or autonomously. Reconfigurability
Classes Static Configuration performed while
device is off line. Dynamic Configuration
device is on-line, "on the fly". Self
Reconfiguration performed autonomously by
device. Evolution type Self Reconfiguration
with adaptation such as replication and growth,
"bio-inspired". ...
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Advantages over competing FPGA and DSP
processors Flexibility ability for
self-reconfiguration Granularity ability to
scale for variable bit-length operations Cost
simpler upgrading of protocols, algorithms, code
schemes Fault Tolerance ability for self repair
and self healing from SEUs Low Power efficient
energy consumption through configuration
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Communication Requirements in Missions

• Rapid adaptation of onboard systems to changing
  environments
• Dynamic communications links
• - self adaptable bandwidth to meet changing
  throughput requirements
• - self managing channel capacity
• Passive communication to reduce power
• Communication Protocol adaptation
• - adapt to changing communication protocols
  for each situation
• Reconfigurable Hardware enabling technology to
  meet these requirements.

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Sensor Web Scenario
Comm Tradeoffs Bandwidth Buffer/Latency
Data Rate, Protocol, ErrorBit Rate.
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Architecture reconfigurable at four Layers
Layer 4 the Adaptation Manager. Layer 3
the Real-Time Operating System RTOS. Layer 2
the Embedded Processors and Memory. Layer
1 the Reconfigurable Hardware Fabric.
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Architecture Non Traditional Reconfigurable
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Reconfiguration Strategy
Occurs at several levels (a) Selection of
application modules by the Adaptation Manager.
(b) Mapping of modules into the hardware fabric
or the embedded processors, depending on
performance requirements. (c) Configuration
of the hardware fabric and the embedded processor
to meet performance and data delivery
requirements. The reconfigurable hardware is
essential for mapping of wireless communications
algorithms such as IR filtering, multichannel
CDMA, complex encoding, advanced imaging.
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Self Adaptation - Dynamic Configuration
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Core Switch Matrix
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Double Buffer Configuration Switch
Cell
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Evolvable Hardware
is capable of on-line adaptation by autonomously
reconfiguring its architecture either through
software or by directly morphing the hardware.
The key idea is to achieve evolution in the
hardware by evolving configuration candidates via
a neural network and testing them for fitness.
A best fit configuration will morph the
hardware to best responding to a particular input
stimulus.
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Evolvable Platform
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Evolution modes
Operation mode NN generates configuration
code Training mode NN incrementally evolves
configurations by training itself on input
stimuli as well as configuration data that are
recurrently applied after being improved by
genetic operations. Other evolution modes e.g.
self-diagnosis and self repair are also feasible.
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Training
During training, candidate configurations are
selected from a population via genetic
operations. Training continues until a
candidate passes a fitness test depending on
responses from the hardware fabric. Training
may start on command or autonomously, in new
environment, new functions or upgrading for
better performance. A major aspect of this
scheme is to design a robust training mechanism
for configuration evolution of the dynamic
hardware fabric.
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Evolvable Hardware Training
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Algorithm Data Flow
Architecture Mapper
Synthesis tools
Arch Resource Netlist
Binding Configurator
Connectivity Bindings
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Synthesis Data Flow transormation of the
application into a resource
graph. Binding allocation of resources
into configurable modules, This
involves functional, local memories and
interconnect modules. Configuration
Core compact description of the
mapping -- in space and
time Loading the configuration matrix into
Buffere FIFOs to employ the mapping.
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Proof of Concept
For proof of concept, we will employ advanced
FPGA boards from Xilinx and Altera, as well as
CAD tools that we have obtained from commercial
vendors.
We will develop an advanced prototyping
environment based on these tools and
software. We will implement by emulation our
proposed reconfigurable hardware on these boards,
without actual chip design. Emulation and
prototyping is quite feasible.