Processor Types and Instruction Sets

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Processor Types and Instruction Sets

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Processor Types and Instruction Sets CS 147 Presentation by Koichiro Hongo Brief Review Of CISC And RISC Complex Instruction Set Computer(CISC) This processor ... –

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Title: Processor Types and Instruction Sets


1
Processor Types and Instruction Sets
  • CS 147 Presentation
  • by
  • Koichiro Hongo

2
Brief Review Of CISC And RISC
  • Complex Instruction Set Computer(CISC) This
    processor includes many
    insturctions and can perform an complex
    computation.
  • Reduced Instruction Set Computer(RISC) This
    prcessor contains a small number of instructions
    that can execute in one clock cycle.

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Other Causes Of Pipeline Stalls
  • Accesses external storage
  • Invoking a coprocessor
  • Branches to a new location
  • Calls a subroutine

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Types Of Operations
  • Arithmetic instructions(integer arithmetic)
  • Logical instructions(also called Boolean)
  • Data access and transfer instructions
  • Conditional and unconditional branch instructions
  • Floating point instructions
  • Processor control instructions

12
An Arithmetic Instruciton Set
Instruction
Meaning ---------------------------------
--------------------------------------------------
-------- add integer addition subtract
integer subtraction add immediate integer
addition(register constant) add
unsigned unsigned integer addition subtract
unsigned unsigned integer subtraction add
immediate unsigned unsigned addition with a
constant move from coprocessor access
coprocessor register multiply integer
multiplication multiply unsigned unsigned
integer multiplication divide integer
division divide unsigned unsigned integer
division move from Hi access high-order
resister move from Lo access low-order
resister
13
Logical(Boolean) And Data Transfer Instruction
Set
Instruction
Meaning ------------------------------------
--------------------------------------------------
----- and logical and(two
resisters) or logical or(two
resisters) and immediate and of resister and
constant or immediate or of resister and
constant shift left logical shift resister
left N bits shift right logical shift resister
right N bits -------------------------------------
Data Tranfer-------------------------------------
load word load resister from memory store
word store resister into memory load upper
immediate place constant in upper
sixteen bits of resister move from
coporoc. resister obtain a value from a
coprocessor
14
Conditional And UnconditionalBranch Instruciton
Set
Instruction
Meaning ------------------------------------
--------------------------------------------------
--------- branch equal branch if two
resisters equal branch not equal branch if two
resisters unequal set on less than compare
two resisters set less than immediate compare
resisters and constant set less than
unsigned compare unsigned resisters set less
than immediate compare unsigned resister and
constant --------------------------------Unconditi
onal Branch---------------------------------- jump
go to target address jump resister go
to address in resister jump and
link procedure call
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The Principle of Orthogonality
  • The principle of orthogonality specifies that
    each instruction should perform a unique task
    without duplicating or overlapping the
    functionality of other instructions.
  • Orthogonality is so important that it has become
    a general principle of processor design.

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Condition Codes And Conditional Branching
On many processors, each instruction produces a
status, which the processor stores in an internal
hardware mechanism. This status that contains
bits to record whether the result is positive,
negative, zero, or an arithmetic overflow
occured is used as condition codes.
A conditional Branch instruction that follows
the arithmetic operation can test one or more of
the condition code bits, and use the result to
determine whereher to branch.
An Example of using a condition code. An ALU
operation sets the condition code, and a later
conditional branch tests the condition code.
Cmp r4, r5 compare regs. 4 5, and set
condition code be lab1 branch to lab1 if
condition code specifies equal mov r3,
0 place a zero in register 3 lab1 ...program
continues at this point
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