Front End Processes

1
Front End Processes
J. Butterbaugh C. Osburn

• ITRS Public Conference
• April 12-13, 2005
• Munich Messe

2
FEP Outline

• Summary of 2004 Updates
• Key Challenges
• Preview of 2005 Roadmap

3
Summary of 2004 Updates Front End Processing

• Back Surface Particle Counts Added to Table
• Based on Experience and Realistic Expectations
• Survey Results Obtained on Gate CD Tolerance
  Components Discrepancies with ITRS Tables Noted
• Industry Not Currently Meeting ITRS
  TolerancesWork Arounds Used
• Gate Dimensions in Resist are Larger than Table
  Values More Aggressive Trimming is Used to Get
  Final Poly Dimension
• Proposal Made for Adjustment in 2005 Table
• Date for Qualification/Preproduction of 300 mm
  SOI Wafers Pulled in from 2006 to 2004
• Reflects Increased Demand from IC Manufacturers
  and Greater Investments by Wafer Manufacturers

4
Summary of 2004 Updates Front End Processing

• Timing of 450 mm Wafer Introduction Highlighted
• 2003 Roadmap Had Dates Ranging from 2011 to 2015
• Note Made that Wafer Manufacturing Development is
  Behind Schedule to Meet 2011 Date
• Lack of Complete Consensus on 450 mm Schedule
  Still Present
• Verification Obtained of Industry Use of Enhanced
  Mobility Channels in 2004
• Validated Equivalent Oxide Thicknesses Values
  from 2003
• Specification of Gate Stack Leakage Refined
• Values are at 100?C
• Values are all Multiples of Device Off-State
  Leakage (Multiple to be Continually Reassessed
  Based on Design Experience)

5
FEP Key Challenges - 1

• Starting Materials
• Site Flatness and Nanotopography
• Chuck wafer / flatness interaction (SEMI)
• Edge exclusion
• Wafer Edge roll-off
• Particles (Size, etc.)
• 450 mm diameter
• Emerging materials
• Surface Preparation
• Cleaning without material loss and pattern damage
• Cleaning and drying deep contacts
• Cleaning low-k materials

6
FEP Key Challenges - 2

• Etch
• Control of gate CD tolerance in aggressive resist
  trim
• Line Edge Roughness
• Thermal
• Low leakage, high channel mobility, reliable
  High-k gate dielectric
• Tunable (dual) work function gate electrodes
• Mobility-enhanced (e.g., strained) channels
• Competing device structures (bulk, UTB SOI,
  multi-gate)
• Shallow trench isolation optimization and
  geometrical control
• Doping
• Series resistance (contact, spreading, and sheet)
• Ultra-shallow junction formation and high dopant
  activation
• Lateral dopant abruptness

7
Starting Materials

• Site Flatness and Nanotopography
• Chuck wafer / flatness interaction (SEMI)
• Edge exclusion
• Wafer Edge roll-off
• Particles (Size, etc.)
• ORTC MPU chip size models to allow two paths
  large chip (800 mm2) and low cost
• FEP defect densities to be based on low cost chip
  size model
• Emerging materials
• SOI
• Strained silicon and strained silicon on
  insulator (sSOI)
• Global strain (wafer supplier)
• Process-induced strain (IDM)
• Film thickness, composition and strain uniformity
• Orientation modification for optimization of CMOS
  electron and hole mobilities
• Implications of multi-gate device structure on
  device characteristics

8
450 mm Wafers

• 450 mm Wafers Required in 2012 (ORTC)
• Introduction of 450 mm presents unprecedented
  challenges
• Technical (meeting specs over larger areas)
• Economic (especially for wafer, equipment, and
  metrology suppliers)
• Critical path definition - We are already late to
  meet this development cycle
• Standardization
• Wafer specification (type, thickness, diameter
  tolerance, etc.)
• Factory automation (load lock, transportation
  method, etc.)
• Wafer package (FOSB, FOUP, door configuration,
  etc.)
• Plan to highlight issues in 2005 ITRS
• FEP subchapter on this topic
• Supplemental white paper
• Inclusion of material in executive summary

9
Yield Model and Front Surface Particles

• Difference in yield models and defect density are
  being investigated by focus team with assistance
  from YE and Starting Materials
• Binomial and Poissons models only diverge when
  defect density is extremely high, at low defect
  density, models track yield
• Concerns arise with respect to die size and die
  size as related to devices type
• Will different device types require different
  yield models? Especially MPU with large dies?
• Focus team is planning to keep status quo in 2005
  and to work with YE to define appropriate
  approach and numbers for 2006
• Plan to get individuals from defect inspection
  company and IC manufacturing companies to help
  with correlation of yield to defect density in a
  fab

10
Back Surface and Edge Particles

• Unclear correlation with yield and back surface
  particles was sited to remove metrics in 2003, IC
  manufacturer data obtained from initial survey in
  2004.
• New survey sent to wider audience in March, 2005
• Additional questions include, cluster particles
  vs. individual particles, edge particles, and
  types of contamination/particles
• 2004 survey showed wide divergence in critical
  defect density, expect same from 2005 survey

11
Repartitioning of Lithography and Etch
Contributions to Physical Gate Length

• Issue Neither Etch nor Lithography Could Meet
  Tolerance Budgets to Achieve /- 10 Control of
  Physical Gate Length
• 2005 Partial Solution
• Maintain Final (Etched) Physical Gate Length at
  2003 Values
• Relax (increase) Printed Gate Length Dimension
  in Resist
• Increase the Amount of Resist Trim
• Repartition Tolerance Budgets from 80 Litho/20
  Etch to
• 75 Litho/25 Etch

Work-Arounds are Still Needed, Since Neither
Litho nor Etch can Meet the Near-Term Tolerance
- Analyses are Being Conducted to Assess the
Impact/Viability of Relaxing Gate CD
Tolerance to /- 12
12
Repartitioning of Lithography and Etch
Contributions to Physical Gate Length

• MPU Physical Gate Length Remains Unchanged from
  2003
• Printed Gate Lengths Will be Larger
• Trim Reduction will be Larger
• Absolute Etch Tolerance Goes up Percent
  Tolerance Goes Down
• Absolute Litho Tolerance Goes Down Slightly, but
  Dimensions are Larger

13
Parallel Lines to Capture Alternative Device
Scenarios

• Extended Bulk Devices to Overlap at least 4 Years
  with UTB SOI / Multi-Gate
• Recognizes Different Approaches in Different
  Companies
• Roadmap will Illustrate Requirements for
  Different Scenarios
• Increases the Number of Lines in the Table
• UTB SOI and multi-gate will be placed on
  separate, over-lapping lines.

14
High k Gate Stacks

• 2005 Equivalent Oxide Thickneses (EOT) to be
  Based on 1D QM Simulations of Capacitance
  Equivalent Thickness (CET) as used in PIDS Device
  Calculations
• Values to be Given for 3E20 (requires specialized
  processing), 2E20 and 1E20 Doping of Poly-Si, and
  Metal Overlapping Entries Illustrate Requirements
  for Alternate Scenarios
• EOT Values to be Limited to 0.4 nm

Example (2005 Values Still in Flux)

• Gate Leakage Requirements are Being Re-evaluated
  with PIDS and Design
• - Static Power Requirements Being Defined
• - Partitioning of Standby Power Between Igate and
  Ioff-device Being Assessed

15
High K Gate Stacks

• High-k precursor purity requirements (with Yield)
• Functional high k properties to be specified
  (thickness, charge levels) until direct tie to
  precursor purity can be established
• Allowable charge in dielectric (1018/cm3)
• Thickness tolerance (4)

16
Memory

• Flash (with IRC and PIDS)
• Industry survey to better quantify feature sizes,
  cell pitch, scaling of inter-poly dielectric,
  etc.
• Good indications that feature size scaling is
  more aggressive than DRAM, so that flash may take
  on characteristics of driver
• DRAM a-factor to be updated (with PIDS)
• Technology node (TN) definitions
• Propose to define FeRAM metrics based on
  stand-alone memory production by 2 suppliers at
  10,000 chips/month
• Other memory technologies to be considered in
  text.

17
Comments / Participation

• Anyone interested in commenting or participating
  in Front End Process, please contact
• Jeff Butterbaugh jeff.butterbaugh_at_fsi-intl.com
• Carl Osburn
• osburn_at_eos.ncsu.edu