Lecture 10 Dynamic Branch Prediction, Superscalar, VLIW, and Software Pipelining

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Lecture 10Dynamic Branch Prediction,
Superscalar, VLIW, and Software Pipelining
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Review Tomasulo Summary

• Register file is not the bottleneck
• Avoids the WAR, WAW hazards of Scoreboard
• Not limited to basic blocks (provided branch
  prediction)
• Allows loop unrolling in HW
• Lasting Contributions
• Dynamic scheduling
• Register renaming
• Load/store disambiguation

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Reasons for Branch Prediction

• For a branch instruction, predict whether the
  branch will actually be TAKEN or NOT TAKEN
• Pipeline bubbles(stalls) due to branch are the
  main source of performance degradation
• Avoids pipeline bubbles by feeding the pipeline
  with the instructions in the predicted
  path(speculative)
• Speculative execution significantly improves the
  performance of the deeply pipelined, wide issue
  superscalar processors
• More accurate branch prediction is required
  because all speculative work beyond a branch must
  be thrown away if mispredicted
• Performancef(Accuracy, cost of misprediction)
• Accuracy is better with Dynamic Prediction

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1-Bit Branch History Table

• Simplest of all dynamic prediction schemes
• Based on the properties that most branches are
  either usually TAKEN or usually NOT TAKEN
• property found in the iterations of a loop
• Keep the last outcome of each branch in the BHT
• BHT is indexed using the lower order bits of PC

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1-Bit Branch History Table
while branch always TAKEN
11111111111111111. for branch TAKEN x 3, NOT
TAKEN x 1 1110111011101110.
Prediction accuracy of for branch 50
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2-Bit Counter Scheme

• Prediction is made based on the last two branch
  outcomes
• Each of BHT entries consists of 2 bits, usually a
  2-bit counter, which is associated with the state
  of the automaton(many different automata are
  possible)

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2-Bit BHT(1)

• 2-bit scheme where change prediction only if
  get misprediction twice
• MSB of the state symbol represents the
  prediction
• 1x TAKEN, 0x NOT TAKEN

Prediction accuracy of for branch 75
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2-Bit BHT(2)

• A branch going unusual direction once causes a
  misprediction only once, rather than twice as in
  the 1-bit BHT
• MSB of the state represents the prediction
• 1x TAKEN, 0x NOT TAKEN

Predict TAKEN
Predict TAKEN
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11
Predict NOT TAKEN
Predict NOT TAKEN
00
01
Prediction accuracy of for branch 75
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2-Level Self Prediction

• First level
• Record previous few outcomes(history) of the
  branch itself
• Branch History Table(BHT) - A shift register
• Second Level
• Predictor Table(PT) indexed by history pattern
  captured by BHT
• Each entry is a 2-bit counter

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2-Level Self Prediction
Algorithm Using PC, read BHT Using self history
from BHT, read the counter value from PT If
(MSB1), predict T else predict NT
After resolving branch outcome, bookkeeping If
mispredicted, discard all speculative
executions Shift right the new branch outcome
into the entry read from BHT Update
PT If(branch outcomeT) increase counter value
by 1 else decrease by 1
Prediction Accuracy 100
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BHT Accuracy

• Mispredict because either
• Wrong guess for that branch
• Got branch history of wrong branch when indexing
  the table
• 4096 entry table, programs vary from 1
  misprediction (nasa7, tomcatv) to 18 (eqntott),
  with spice at 9 and gcc at 12
• 4096 about as good as infinite table, but 4096 is
  a lot of HW

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Correlating Branches
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Correlating Branches

• Idea TAKEN/NOT TAKEN of recently executed
  branches (GHR-global history) is related to the
  behavior of the next branch (as well as the
  history of that branch behavior)(PHT-self
  history)

- Behavior of the recent branches(GHR) selects
from, say, four predictions (PHT) of the next
branch, and updating the selected prediction only
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Correlating Branches
Misprediction only in the firest two predictions
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Accuracy of Different Schemes
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Need Predicted Address as well as Prediction

• Branch Target Buffer (BTB) Indexed by the
  Address of branch to get prediction AND branch
  address (if taken)

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Branch Target Buffer
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(No Transcript)
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Getting CPI lt 1 Issuing Multiple
Instructions/Cycle

• Two variations
• Superscalar varying number of instructions/cycle
  (1 to 8), scheduled by compiler or by
  HW(Tomasulo)
• IBM PowerPC, Sun SuperSparc, DEC Alpha, HP 7100
• Very Long Instruction Words (VLIW) fixed number
  of instructions (16) scheduled by the compiler
• Joint HP/Intel agreement in 1998?

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Getting CPI lt 1 Issuing Multiple
Instructions/Cycle

• Superscalar DLX 2 instructions, 1 FP 1
  anything else
• Fetch 64-bits/clock cycle Int on left, FP on
  right

• Can issue the 2nd instruction only if the 1st
  instruction issues
• More ports for FP registers to do FP load FP
  op in a pair

• 1 cycle load delay expands to 3 instructions in
  SS
• instruction in right half cannot use it, nor
  instructions in the next slot

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Unrolled Loop that Minimizes Stalls for Scalar
1 Loop LD F0,0(R1) 2 LD F6,-8(R1) 3 LD F10,-16(R1
) 4 LD F14,-24(R1) 5 ADDD F4,F0,F2 6 ADDD F8,F6,F2
7 ADDD F12,F10,F2 8 ADDD F16,F14,F2 9 SD 0(R1),F4
10 SD -8(R1),F8 11 SUBI R1,R1,32 12 SD 16(R1),F1
2 13 BNEZ R1,LOOP 14 SD 8(R1),F16 8-32 -24
Loop LD F0, 0(R1) ADDD
F4, F0, F2 SD 0(R1), F4
SUBI R1, R1, 32 BNEZ
R1, Loop
LD to ADDD 1 Cycle ADDD to SD 2 Cycles
14 clock cycles, or 3.5 per iteration
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Loop Unrolling in Superscalar

• Integer instruction FP instruction
  Clock cycle
• Loop LD F0,0(R1) 1
• LD F6,-8(R1) 2
• LD F10,-16(R1) ADDD F4,F0,F2 3
• LD F14,-24(R1) ADDD F8,F6,F2 4
• LD F18,-32(R1) ADDD F12,F10,F2 5
• SD 0(R1),F4 ADDD F16,F14,F2 6
• SD -8(R1),F8 ADDD F20,F18,F2 7
• SD -16(R1),F12 8
• SUBI R1,R1,40 9
• SD 16(R1),F16 10
• BNEZ R1,LOOP 11
• SD 8(R1),F20 12

• Unrolled 5 times to avoid delays (1 due to 2
  cycle initiation delay for ADDD to SD)
• 12 clocks, or 2.4 clocks per iteration

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Dynamic Scheduling in Superscalar

• Dependencies stop instruction issue
• Code compiled for scalar version will run poorly
  on SS
• Good code for superscalar depends on the
  structure of the superscalar
• Simple approach
• Issue an integer instruction and a FP instruction
  to their separate reservation stations, i.e. for
  Integer FU/Reg and for FP FU/Reg
• Issue both only when two instructions do not
  access the same register - instructions with data
  dependence cannot be issued together

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Dynamic Scheduling in Superscalar

• How to issue two instructions to the reservation
  stations and keep in-order issue for Tomasulo?
• In order issue for the purpose of simplifying
  bookkeeping
• Issue stage runs 2X Clock Rate, so that issue can
  be made 2 times in an ordinary clock cycle to
  make issues remain in order but execution can be
  done on the same ordinary clock cycle
• Only FP loads might cause dependency between
  integer and FP issue
• Replace load reservation station with a load
  queue operands must be read in the order they
  are fetched
• Load checks addresses in Store Queue to avoid RAW
  violation
• Store checks addresses in Load Queue to avoid
  WAR, WAW

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Performance of Dynamic SS

• Iter No. Issues Executes
  Memory access Write Result
• 1 LD F0,0(R1)
• 1 ADDD F4,F0,F2
• 1 SD 0(R1),F4
• 1 SUBI R1,R1, 8
• 1 BNEZ R1,LOOP
• 2 LD F0,0(R1)
• 2 ADDD F4,F0,F2
• 2 SD 0(R1),F4
• 2 SUBI R1,R1,8
• 2 BNEZ R1,LOOP

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1
4
2(efa)
7
4
1
2 more cycles to complete
3(efa)
2
6
5
3
4
4
5
5
8
7
6(efa)
11
8
2 more cycles to complete
5
10
7(efa)
6
9
8
7
8
9
4 clocks per iteration Branches, Decrements
still take 1 clock cycle
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Limits of Superscalar

• While Integer/FP split is simple for the HW, get
  CPI of 0.5 only for programs with
• Exactly 50 FP operations
• No hazards
• If more instructions issue at the same time,
  greater difficulty of decode and issue
• Even 2-scalar gt examine 2 opcodes, 6 register
  specifiers, decide if 1 or 2 instructions can
  issue
• VLIW trade-off instruction space for simple
  decoding
• The long instruction word has room for many
  operations
• By definition, all the operations the compiler
  puts in the long instruction word can execute in
  parallel
• E.g., 2 integer operations, 2 FP ops, 2 Memory
  refs, 1 branch
• 16 to 24 bits per field gt 7x16 or 112 bits to
  7x24 or 168 bits wide
• Need compiling technique that schedules across
  several branches

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Loop Unrolling in VLIW

• Memory Memory FP FP Int. op/ Clockreference 1
  reference 2 operation 1 op.
  2 branch a
• LD F0,0(R1) LD F6,-8(R1) 1
• LD F10,-16(R1) LD F14,-24(R1) 2
• LD F18,-32(R1) LD F22,-40(R1) ADDD F4,F0,F2 ADDD
  F8,F6,F2 3
• LD F26,-48(R1) ADDD F12,F10,F2 ADDD F16,F14,F2 4
• ADDD F20,F18,F2 ADDD F24,F22,F2 5
• SD 0(R1),F4 SD -8(R1),F8 ADDD F28,F26,F2 6
• SD -16(R1),F12 SD -24(R1),F16 7
• SD -32(R1),F20 SD -40(R1),F24 SUBI R1,R1,48 8
• SD 0(R1),F28 BNEZ R1,LOOP 9

• Unrolled 7 times to avoid delays
• 7 results in 9 clocks, or 1.3 clocks per
  iteration
• Need more registers in VLIW

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Limits to Multi-Issue Machines

• 1. Inherent limitations of ILP in programs
• 1 branch in 5 instructions gt how to keep a 5-way
  VLIW busy?
• Latencies of units gt many operations must be
  scheduled
• Need about Pipeline Depth x No. Functional Units
  of independent operations to keep machines busy
• 2. Difficulties in building HW
• Duplicate FUs to get parallel execution
• Increase ports to Register File - VLIW example
• needs 6 reads(2 Integer Unit, 2 LD Units and 2 SD
  Units) and 3 writes(1 Integer Unit and 2 LD
  Units) for Int. register
• needs 6 reads(4 FP Units, 2 SD Units) and
  4 writes(2 FP Units
  and 2 LD Units) for FP register
• Increase ports to memory
• Decoding SS and impact on clock rate, pipeline
  depth

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Limits to Multi-Issue Machines

• 3.Limitations specific to either SS or VLIW
  implementation
• Multiple issue logic in SS
• VLIW code size unroll loops wasted fields in
  VLIW
• VLIW lock step gt 1 hazard all instructions
  stall
• VLIW binary compatibility is practical weakness

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Detecting and Eliminating Dependencies

• Read Section 4.5

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Software Pipelining

• Observation if iterations from loops are
  independent, then can get ILP by taking
  instructions from different iterations
• Software pipelining reorganizes loops so that
  each iteration is made from instructions chosen
  from different iterations of the original loop
  (Tomasulo in SW)

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SW Pipelining Example

• Before Unrolled 3 times
• 1 LOOP LD F0,0(R1)
• 2 ADDD F4,F0,F2
• 3 SD 0(R1),F4
• 4 LD F6,-8(R1)
• 5 ADDD F8,F0,F2
• 6 SD -8(R1),F8
• 7 LD F10,16(R1)
• 8 ADDD F12,F10,F2
• 9 SD -16(R1),F12
• 10 SUBI R1,R1,24
• 11 BNEZ R1,LOOP

After Software Pipelined version of loop LD
F0,0(R1) ADDD F4,F0,F2 LD F0,-8(R1) 1
LOOP SD 0(R1),F4 Stores to Mi 2 ADDD
F4,F0,F2 Adds to Mi-1 3 LD
F0,-16(R1) Loads from Mi-2 4 SUBI
R1,R1,8 5 BNEZ R1,LOOP SD
0(R1),F4 ADDD F4,F0,F2 SD -8(R1),F4
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SW Pipelining Example

• Symbolic Loop Unrolling
• Less code space
• Overhead paid only once vs. each iteration
  in loop unrolling

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Summary

• Branch Prediction
• Branch History Table 2 bits for loop accuracy
• Correlation Recently executed branches
  correlated with next branch
• Branch Target Buffer include branch address
  prediction
• Superscalar and VLIW
• CPI lt 1
• Dynamic issue vs. Static issue
• More instructions issue at the same time, larger
  the penalty of hazards
• SW Pipelining
• Symbolic Loop Unrolling to get most from pipeline
  with little code expansion, little overhead
• SW pipelining works when the behavior of branches
  is fairly predictable at compile time