Lecture 6 - Writing Tests

1
Lecture 6 - Writing Tests

• A difference if treating the design as a black
  box or if you have access to internal signals
• EE762 assignment testbenches treat student design
  as a black box
• Must know what you are testing
• Must test corner cases

2
Floating Point Multiplier

• Used as a EE762 assignment

Project Assignment 10 Floating Pt Unit DUE Mon
Mar 10   In this assignment you will use VHDL to
describe the function of a floating point
multiplier. The multiplier will accept IEEE
Standard 754 single precision inputs and produce
single precision output. It will support NaN,
8, 0, normalized numbers, and denormalized
numbers.   The interface to the design will be
3
The Assignment
Inputs will arrive as per the attached
specification and test bench. Your design will
latch inputs using the latch input signal. Your
design will drive the outputs using the drive
signal. After driving the output, when the drive
signal again goes high, you must drive the bus
back to high impedance. Use the component
interface given in the testbench STEP 1) Write
the initial architecture. In the initial
architecture, simply latch the input, route the A
input to the output, and correctly drive the C
bus. If you get this step working correctly the
rest will go much easier. SIMULATE   STEP 2)
Write a VHDL process to do the floating point
multiply.   Recommendation As you start to
write your routine handle special cases first.
Write the code to handle the NaNs - then simulate
and check that you handle the NaNs correctly.
Note that 8 0 results in a NaN.. Then
correctly handle 8, and verify through
simulation. Then correctly handle 0 and
simulate. Finally do the cases where you
actually have to multiply.   You can use
process(es), concurrent signal assignment, etc.,
as you would like. You will find the following
files in degroat/ee762_assign   fpmtb.vhdl -
the test bench - the component declaration,
configuration,and instantiation have been done
but you can change them if you want
to.   fpmvectors - a list of the input stimul
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The Assignment (2)
fpm.do - do file for listing and
waveform   Other NOTES for floating point
multiplier.   The test bench also uses a
concurrent procedure call that reads the
testvector file in degroat/ee762_assign/fpmvecto
rs. Use of these vectors is hard coded in the
concurrent procedure as are the checks and
grading routine. This procedure has been
compiled and is in the library assign in this
directory. To provide the mapping to it you must
execute the unix command   qhmap assign
/user2/faculty/degroat/ee762_assign/assign   This
provides the logical mapping such that the
library clause in the test bench know where
library assign is located. This must be done
prior to compiling the test bench. The procedure
will also do the grading of this assignment.
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Floating Point Standard
Single Precision Floating Point Format Value
is If e 255 and f ? 0, then v is NaN
regardless of s If e 255 and f 0, then v
(-1)s 8 If 0 lt e lt 255, then v (-1)s
2e-127 (1.f) If e 0 and f ? 0, then v
(-1)s 2-126 (x.f) (denormalized
numbers)(x is msb of value stored) If e 0 and
f 0, then v (-1)s 0 (zero)
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Other Specifications

• Inputs are in IEEE 754 Single Precision
• Results are in IEEE 754 Single Precision Format
• Unit can latch A and B inputs from parallel
  busses
• Must be able to handle both numerical values and
  special cases
• NaNs, inif,
• zero,
• normalized numbers, denormalized numbers

7
What to Check

• How to test the floating point multiplier for
  both timing of inputs and outputs and functional
  operation?
• Assume you have no knowledge of how design is
  going to be implemented
• But you still know the specifications that it
  must adhere to.

8
The Test Vectors
Must test for normal operation and boundary
conditions  IN GENERAL THE CLASS OF INPUTS
ARE A input by B input NaN NaN 8 8 0 0
Denorm Denorm Norm Norm   Denorm
OtherVal Max Denorm Denorm OtherVal Min
Norm Rounding using first guard
bit Rounding using 1st and 2nd guart bits
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The Inputs Example 1
...NaN 01111111100000000000000000000001...NaN
01111111100000000000000000000001...Nan
01111111100000000000000000000001...NaN
01111111100000000000000000000001.INIF
01111111100000000000000000000000...Nan
01111111100000000000000000000001...NaN
01111111100000000000000000000001.-INIF
11111111100000000000000000000000...Nan
01111111100000000000000000000001...NaN
01111111100000000000000000000001....0
00000000000000000000000000000000...Nan
01111111100000000000000000000001...NaN
01111111100000000000000000000001....-0
10000000000000000000000000000000...Nan
01111111100000000000000000000001...NaN
01111111100000000000000000000001....1
00111111100000000000000000000000...Nan
01111111100000000000000000000001...NaN
01111111100000000000000000000001....-1
10111111100000000000000000000000...Nan
01111111100000000000000000000001...NaN
01111111100000000000000000000001...25
01000001110010000000000000000000...Nan
01111111100000000000000000000001...NaN
01111111100000000000000000000001...-25
11000001110010000000000000000000...Nan
01111111100000000000000000000001...NaN
01111111100000000000000000000001..100
01000010110010000000000000000000...Nan
01111111100000000000000000000001...NaN
01111111100000000000000000000001.1/100
00111100001000111101011100001010...Nan
01111111100000000000000000000001...NaN
01111111100000000000000000000001DNORM
00000000001010000000000000000000...Nan
01111111100000000000000000000001...NaN
01111111100000000000000000000001-DNORM
10000000001010000000000000000000...Nan
01111111100000000000000000000001.INIF
01111111100000000000000000000000...NaN
01111111100000000000000000000001...NaN
01111111100000000000000000000001
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The Inputs Example 2
...25 01000001110010000000000000000000....0
00000000000000000000000000000000....0
00000000000000000000000000000000...25
01000001110010000000000000000000....-0
10000000000000000000000000000000....-0
10000000000000000000000000000000...25
01000001110010000000000000000000....1
00111111100000000000000000000000...25
01000001110010000000000000000000...25
01000001110010000000000000000000....-1
10111111100000000000000000000000...-25
11000001110010000000000000000000...25
01000001110010000000000000000000...25
01000001110010000000000000000000..625
01000100000111000100000000000000...25
01000001110010000000000000000000...-25
11000001110010000000000000000000..-625
11000100000111000100000000000000...25
01000001110010000000000000000000..100
01000010110010000000000000000000.2500
01000101000111000100000000000000...25
01000001110010000000000000000000.1/100
00111100001000111101011100001010.0.25
00111110011111111111111111111111...25
01000001110010000000000000000000DNORM
00000000001010000000000000000000small1
00000001111110100000000000000000...25
01000001110010000000000000000000-DNORM
10000000001010000000000000000000small2
10000001111110100000000000000000...-25
11000001110010000000000000000000...NaN
01111111100000000000000000000001...NaN
01111111100000000000000000000001...-25
11000001110010000000000000000000.INIF
01111111100000000000000000000000.-INIF
11111111100000000000000000000000...-25
11000001110010000000000000000000.-INIF
11111111100000000000000000000000.INIF
01111111100000000000000000000000...-25
11000001110010000000000000000000....0
00000000000000000000000000000000....-0
10000000000000000000000000000000
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Applying Inputs to Design
WHILE (NOT ENDFILE(test_data)) LOOP --get
next input test vector and expected result
readline(test_data,cur_line)
read(cur_line,aid) read(cur_line,a_test_val)
read(cur_line,bid) read(cur_line,b_test_val)
readline(test_data,cur_line)
read(cur_line,resid)read(cur_line,result_val)
std_result_val To_StdLogicVector(result_val)
num_tests num_tests 1 -- run
through bus cycle to send data to unit
aid_sig lt "", aid after 20 ns
bid_sig lt "", bid after 20 ns
resid_sig lt "", resid after 20 ns --
drive signals on bus aval lt
To_StdLogicVector(a_test_val) after 20 ns, HIGHZ
after 80 ns bval lt To_StdLogicVector(b_test_
val) after 20 ns, HIGHZ after 80 ns latch lt
'0' after 20 ns, '1' after 70 ns wait for
100 ns drive lt '0' after 20 ns, '1' after
80 ns exp_res lt std_result_val after 20 ns,
HIGHZ after 80 ns wait for 50 ns ASSERT
(C std_result_val) REPORT "result does
not agree with expected result" SEVERITY
WARNING IF (C / std_result_val) THEN
num_errors num_errors 1 err_sig lt
'1', '0' after 10 ns END IF wait for 50
ns END LOOP
Inputs are read from a file and applied to the
design
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The File I/O Declarations

• First must set up the basic declarations

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File I/O

• And then must also do the declarations for File
  I/O
• Note that the file I/O here uses the 1987 version
  of the language

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Checking Results

• Timing is checked when result is expected on bus
  and again just prior to bus going back to high
  impedance.
• Busses are also checked that they go back to a
  value of high impedance
• When results do not match what is expected a
  signal called error goes to 1 for 10 ns

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Use of TEXT IO

• The TEXT IO procedures and functions are in
  PACKAGE TEXTIO within LIBRARY STD.
• So any design entity that wants to do IO using
  these routines must have a
• USE STD.TEXTIO.ALL
• You will find a reference in Navabi, pg 603,604.

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TEXT IO Philosophy

• The general input/output philosophy of VHDL is
  one of line orientated operation.
• For Input you first read the entire line up until
  ltcrgtltlfgt
• Same for output
• Then you read the elements off the line.
• For the file here the elements were
• AID A_FP_NUM BID B_FP_NUM

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Type that can be read/written using TEXT I/O

• The data types for which support is present
• Strings
• Bit
• Bit_vector
• Integer
• Read

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Example 1

• use std.textio.all
• ENTITY textiotest IS
• END textiotest
•  
• ARCHITECTURE first OF textiotest IS
•  
• FILE test_vecs TEXT is "fpmvectors"
• SIGNAL a,b bit_vector(31 downto 0)
• signal aid,bid string(1 to 6)

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Example 1 (cont)

• BEGIN --of architecture
•  
• PROCESS
• VARIABLE cur_line LINE
• VARIABLE aidv,bidv string(1 to 6)
• VARIABLE av,bv bit_vector(31 downto 0)
• BEGIN
• FOR I in 1 to 10 LOOP
• READLINE (test_vecs, cur_line)
• READ (cur_line,aidv)
• aid lt aidv
• READ (cur_line,av)
• a lt av
• READ (cur_line,bidv)
• bid lt bidv
• READ (cur_line,bv)
• b lt bv
• WAIT FOR 100 ns

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Example 2

• use std.textio.all
• ENTITY textiotest2 IS
• END textiotest2
•  
• ARCHITECTURE first OF textiotest2 IS
• FILE test_vecs TEXT is "fpmvectors"
• SIGNAL a,b,r bit_vector(31 downto 0)
• signal aid,bid,rid string(1 to 6)
• BEGIN

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Example 2 (cont)

• PROCESS
• VARIABLE cur_line LINE
• VARIABLE aidv,bidv,ridv string(1 to 6)
• VARIABLE av,bv,rv bit_vector(31 downto
  0)
• BEGIN
• WHILE (NOT ENDFILE(test_vecs)) LOOP
• READLINE (test_vecs, cur_line)
• READ (cur_line,aidv)
• aid lt aidv
• READ (cur_line,av)
• a lt av
• READ (cur_line,bidv)
• bid lt bidv
• READ (cur_line,bv)
• b lt bv
• READLINE (test_vecs, cur_line)
• READ (cur_line,ridv)
• rid lt ridv

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Test transactions are in file

• Locating you test transactions in a file allows
  for easy addition to the test file as you
  progress through the verification plan
• Allows you to incorporate new tests easily based
  on the results to date.
• Opens the possibility for very advanced methods
• Interative application of tests and test
  generation.
• New tests may be generated given the response to
  a set test.