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Tallinn University of Technology

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Title: Artec Design Group Author: jaan Last modified by: Ubar Created Date: 11/29/2004 10:05:14 AM Document presentation format: On-screen Show Company – PowerPoint PPT presentation

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Title: Tallinn University of Technology


1
Tallinn University of Technology
  • Founded as engineering college in 1918, TTU
    acquired university status in 1936.
  • TTU has about 9000 students and 1209 employees,
    offering engineering and economics diploma
    studies, bachelor, master and doctorate degree
    programmes.
  • Academic part of the university is organised into
  • 8 faculties,
  • 30 departments and 108 chairs,
  • 7 centres and
  • 9 affiliated institutions.

Raimund Ubar Computer Engineering Department
2
Research Topics
  • Computer science Decision Diagrams
  • Test Pattern Generation
  • Hierarchical Approaches
  • Defect-Level Testing
  • Simulation of Circuits and Systems
  • Fault Simulation (SAF, functional faults, delays)
  • Dynamic (multivalued) Simulation
  • Built-In Self-Test
  • Hybrid BIST
  • Functional BIST
  • Hardware accelerators for Fault Simulation

3
European projects
  • History (1992-2000)
  • TEMPUS Digital Design based on PLDs (1992-95)
  • EUROCHIP (1993 -1996) - EUROPRACTICE (1996 -)
  • PECO EEMCN - East European Microelectronics
    Cooperation Network (1993-96)
  • COPERNICUS FUTEG - Functional Test Generation
    (1994-97)
  • ESPRIT ATSEC - Advanced Test Generation and
    Testable Design Methodology (1994-96)
  • COPERNICUS SYTIC - System Design Training
    (1996-98)
  • COPERNICUS VILAB - Microelectronics Virtual
    Laboratory for Cooperation in Research
    (1998-2002)

4
Current European Projects
  • FRAMEWORK V REASON - Research and Training
    Action for System On Chip Design (2002-2004)
  • FRAMEWORK V eVikings II - Establishment of the
    Virtual Centre of Excellence for IST RTD in
    Estonia
  • SOCRATES 2 Thematic Network Project THEIERE
    -Thematic Harmonisation in Electrical and
    Information EngineeRing in Europe
  • SOCRATES 2 Thematic Network Project ECET -
    European Computing Education and Training
    (2002-2004)
  • EUROPRACTICE

5
Our Partners
TTU cooperates with about 20-30 universities
KTH
LIU
TTU
Jonköping
USA Michigan U
Dresden
East- and Middle-Europe
Kharkov
Ilmenau
Costa Rica
Darmstadt
Stuttgart
Grenoble
Indonesia
Torino
6
Hierarchical Test Generation Tool
7
Turbo-Tester Tool Set
8
Hybrid BIST for Multiple Cores
Embedded tester for testing multiple cores
9
Optimized Multi-Core H-BIST
Pseudorandom test is carried out in parallel,
deterministic test - sequentially
10
Applet for Learning RT L Test
  • For learning problems of RT-level digital design
    and test
  • Design of data path and control path
  • Tradeoffs between speed HW cost
  • RT-level simulation
  • Fault simulation
  • Test generation
  • DFT and BIST

11
Virtual Lab Tool integration
Cooperation with Fh-IIS, DTU, LIU, IISAS, WUT
12
Proposal Ingredients of SoC test
  1. Functional test to test the system (WP1)
  2. BIST, embedded test for IP cores (WP3)

13
Tallinn University of Technology
  • WP1. High-level modeling and simulation
  • Methods for automated generation of functional
    test at the system-level for verification
    purposes.
  • We have previous experience in
  • High-level modeling and simulation
  • High-level test pattern generation
  • Design error identification at the logic level.

14
Tallinn University of Technology
  • WP3. Setting up a Virtual IP library
  • Solutions for automated synthesis of the test
    infrastructure to IPs.
  • Novel hybrid BIST strategies
  • Functional BIST
  • Web based e-learning tools for teaching IP test
    standards like Boundary scan and P1500.

15
Artec Design Group
  • Artec Design Ltd. founded in 1998 is a successful
    Estonian SME empoying more than 30 people.
  • In 2001, the company was selected to top ten in
    the Central European Technology Fast list.
  • The field of the Artec company is designing
    hardware, ASICs, embedded software and factory
    information systems.
  • The company has been involved in a number of
    national and European level research projects.
  •  

16
Artec Design Group
  • VPNow an IP core for cryptographic network
    processing.
  • It allows any system with PCI interface to
    connect using the IPSec encryption standard.
  • Possible to send new, ipv6 internet protocol
    packets via existing ipv4 networks and
    vice-versa.
  • A network-ready, full-function compact 486
    motherboard with an award-winning Single
    Component Computer MachZ.
  •  
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