TFT LCD AIM SPICE

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TFT LCD AIM SPICE
P92943013 / ??? P91943014 / ???
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Past History of SPICE

• SPICE Simulation Program with Integrated
  Circuit Emphasis
• 1968 Ron Rohrer Berkeley,Larry Nagel? CANCER
• 1970 SPICE1(Fortran)
• 1975 SPICE2(Fortran)
• 1980 SPICE3(C Language)
• 1980Now
• HSPICE
• PSPICE
• AIM-SPICE (AIM)
• Smart-SPICE (Silvaco)
• Eldo (Mentor)
• Spectre (Cadence)

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SPICE Algorithms
Principle Kirchhoffs Law
node
Numerical analysis Newton Method
4
Analog Circuit Design Flow
Schematic edit
Circuit simulation SPICE
Schematic driven layout
Layout -Laker
Device model extraction 1. TEG data analysis 2.
Curve fitting 3. Process characterization
DRC/LVS -Calibre
No
Yes
Post simulation SPICE
Parasitic R/C Extractor -Calibre RCX
GDS II / Mask
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AIM SPICE Parameter Extract_1
TFT LCD Test Mask IV Curve
IdVd Curve Vg 5V,10V,15V,20V,30V
IdVg Curve Vd 1V,4V,7V,10V,13V
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AIM SPICE Parameter Extract_2
Hole-Induced Leakage Current
Above Threshold
Below Threshold
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AIM SPICE Parameter Extract_3
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Pixel Equal Circuit RC Calculation
Cgate ((CstClc)/(Cst Clc) Cgs Cgs_coup
Cdg cross Cgate_com)12803
Rgate (? L1/W1)12803
Cdata Cgd Cdg cross Cdata_com
Cpixel_data_coup)1024
Rdata(? L2/W2)1024
Cpixel Cgs Cgs_coup Clc Cst
Cpixel_data_coup
Data Line the N-1th
Data Line the N th
Gate Line the (N-1)th
C st(on gate)
C lc
2
1
C pixel_data coup(own)
9
C data_com ( lc )
6
C pixel_data coup(next)
10
Gate Line the Nth
C gs
C gd
C gs_coup
8
3
4
C gate_com
5
C dg cross
7
9
Using Pi(p) Model to Simulated
We using 4 p Model to simulated one gate line and
data line
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Panel Equal Circuit of Simulation
If Resolution 12801024 Node 3 Sub_pixel
(0,512) Node 4 Sub_pixel (1920,512) Node 5
Sub_pixel (3840,512)
Signal in
1
14
V
Driving Direction
Gate n-1 Pulse
2
10
11
12
V
23
26
Gate n Pulse
3
4
5
V
17
20
6
7
8
9
9
9
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SPICE Program Description 1 - Basic Definition
(DeviceName) Node Value / Parameter
Device D Diode C Capacitance I Independent
Current Source J JFET M MOS Q BJT R
Resister V Independent Current Source
ex Rgate 1 3 25k Cgate 1
3 25p Vgate 1 3 25V M1 2(D)
3(G) 6(S) 0(GND) Model()
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SPICE Program Description 2 - Basic Definition
Dot Command Format gt . command
.DC ???? .END ???? .IC
???????? .MODEL MODEL?? .PLOT
???? .PRINT ???? .TRAN ????
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SPICE Program Description 3 Power definition
VGATE1 3 0 PWL 0u vgl 25u vgl 25.01u vgh 35.31u
vgh 35.32u vgl 150u vgl VSIG1 2 0 PULSE
(vdl vdh 12.5u 1n 1n 12.499u
25u) V1 V2
start rise fall pulse width
period VCOM2 9 0 5V 5V DC voltage
source
V2
V1
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SPICE Program Description 4 - Example 1
Simulation of One Gate Delay by AIM-Spice
.param vgh27V vgl-6V vgc-6V .param
gpi_r1.176k gpi_c24.27p .param
gpx_r0.3k .param length9u width18u VGATE1 3 0
PWL 0u vgl 25u vgl 25.01u vgh 35.31u vgh 35.32u
vgl 150u vgl .IC V(10)vgl V(3)vgl GATE
DELAY 0 Drive IC RGATE01 0 3
gpx_r CGATE01 0 3 2.5p CGATE02 0 10
2.5p GATE DELAY 1 PI-g1 RGATE11
3 6 gpi_r RGATE12 6 4 gpi_r CGATE11 3 0
gpi_c CGATE12 6 0 gpi_c2 CGATE13 4 0 gpi_c
GATE DELAY 2 PI-g2 RGATE21 4 7
gpi_r RGATE22 7 5 gpi_r CGATE21 4 0
gpi_c CGATE22 7 0 gpi_c2 CGATE23 5 0
gpi_c .TRAN 1.000000e-07 100u .PLOT TRAN V(3)
V(4) V(5) .END
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SPICE Program Description 5 - Model - 1
General form MXXXXXXX ND NG NS NB MNAME
ltLVALUEgt ltWVALUEgt ltADVALUEgt ltASVALUEgt
ltPDVALUEgt ltPSVALUEgt ltNRDVALUEgt ltNRSVALUEgt
ltOFFgt ltICVDS,VGS,VBSgt ltTEMPTgt
a-Si TFT in SMART SPICE .MODEL