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Ender YILMAZ, Hasan Tahsin OGUZ

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Reconfigurable Computing Ender YILMAZ, Hasan Tahsin O UZ Overview Energy savings are in average 35% to 70%, and speedup is in average 3 to 7 times. – PowerPoint PPT presentation

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Title: Ender YILMAZ, Hasan Tahsin OGUZ


1
Reconfigurable Computing
  • Ender YILMAZ, Hasan Tahsin OGUZ

2
Overview
  • Energy savings are in average 35 to 70, and
    speedup is in average 3 to 7 times.
  • Reduction in size and component
  • Time to market
  • Flexibility and upgradability

3
Three ways of supporting processing requirements
  • High performance microprocessors
  • Even expensive µPs are not fast enough for many
    applications
  • Power consumption(100W or more)
  • Not convenient for embedded applications
  • Application specific ICs (ASICs)
  • Provides a natural mechanism for large amount of
    parellalism
  • Does not suffer from serial instruction fetch
  • Consumes less power than reconfigurable devices
  • Not general purpose
  • Time to market
  • Infeasable for many embedded systems, only high
    volume of production makes it feasible

4
Three ways of supporing processing
requirements(continued)
  • Reconfigurable Computing
  • In the middle of µP and ASICs as performance and
    power consumption
  • Parellalism due to hardware implementation
  • Cheaper for low volume production
  • Design time and time to market is much less
  • Functional units can change over time
  • General Purpose

5
System Level Architectures
Five classes of reconfigurable systems a External
stand-alone processing unit b Attached processing
unit c Co-processor d Reconfigurable functional
unit e Processor embedded in a reconfigurable
fabric
6
System Level Architectures
7
Reconfigurable Fabric
  • consists of reconfigurable functional units,
    reconfigurable interconnect and a flexible
    interface to the rest of the system
  • There is a tradeoff between flexibility and
    efficiency.

8
Functional Units
  • Fine Grained implements functions for single or
    small number of bits
  • Coarse Grained larger, ALU, DSP

9
Emerging Directions
  • Low power techniques
  • Activity reduction in power-aware design tools
  • Leakage current reduction
  • Dual supply voltage methods
  • Asynchronous architectures
  • Fine grained asynchronous pipelines
  • Quasi delay insensitive architectures
  • Globally async. Locally sync.
  • Molecular microelectronics
  • Promising for increasing capacity and performance
    of reconf. Comp. Arch.

10
Main Trends in Architectures
  • Coarse grained fabrics
  • Cost of interconnection is increasing due to
    advancements in tech., granularity of LUs are
    increasing to reduce routing overhead
  • Heterogeneous functions
  • Due to migration to more advanced tech., number
    of transistors devoted to the reconf. logic
    increases. Multipliers , DSP units can be added
  • Soft cores
  • Instructions are programmable
  • Although being less area and speed efficient,
    flexible

11
Design Methods
  • Hardware compilers for high-level descriptions
    are key to reduce the productivity gap for
    advanced circuit development
  • Design methods can be generally categorized into
    two general design methods and special design
    methods
  • General purpose designs
  • Annotation and constraint driven approach
  • Source-directed compilation approach
  • Special purpose design
  • Digital Signal Processing
  • The word-length optimisation
  • Other Design Methods
  • Run time customisation
  • Soft instruction processor
  • Multi FPGA compilation

12
General Purpose Design
  • Design methods and tools are based on general
    purpose programming languages such as C, C and
    Java
  • HDLs VHDL and Verilog are also available
  • A number of compilers from C to hardware have
    been developed
  • Target hardware or hardware/software
  • Two different approached
  • Annotation and constraint driven approach
  • Annotations are used in source-code constraint
    files
  • Only minor changes are needed to produce a
    compilable program from software description
  • Source-directed compilation approach
  • Source languages are adopted to enable explicit
    description of parellelism, communication and
    other customisable hardware resources

13
Summary of General Purpose Hardware Compilers
14
Special Purpose Design
  • There are many specific problem domains which
    deserve special consideration
  • Exploiting domain specific properties
  • Describe the computation (MATLAB-Simulink)
  • Optimise the implementation
  • Digital Signal Processing
  • The word-length optimisation

15
Digital Signal Processing
  • One of the most successful applications for
    reconfigurable computing is real-time digital
    signal processing(DSP)
  • Inclusion of hardware support for DSP in FPGA
  • DSP problems share similar properties
  • Algorithms are numerically insensitive but have
    very simple control structures
  • Controlled numerical error is acceptable
  • SNR exist for measuring numeric precision
  • Design is performed in Simulink
  • Designer need not deal with low level
    implementation issues

16
The word-length optimisation
  • Unlike mP based implementations size of each
    variable is customisable.
  • Numerical accuracy, design size, speed and power
    cons.
  • Most important decision is selection of an
    appropriate word-length and scaling for each
    signal
  • The accuracy is less sensitive to some variables
    than to others
  • Considering error and area information, it is
    possible to achieve a highly efficient DSP
    implementation
  • Word-length optimisation problem is NP-hard
  • Heuristics are used, area/signal quality tradeoff
  • Analytic methods are faster but pessimistic

Area Speedup
Bitwise 15-56 65
MATCH 80 20
WadekerParker 15-40
Bitsize 20-30
17
Other Design Methods
  • Run-time customisation
  • Soft instruction processors
  • Multi-FPGA compilation

18
Run-time customisation
  • One part of the system continues to be
    operational, while other part is being
    reconfigured
  • At compile time, an initial configuration
    bitstream and incremental bitstreams have to be
    produced
  • Runtime design optimisation techniques
  • Runtime constraint propagation, producing a
    smaller circuit with higher performance by
    boolean algebra optimisation
  • Library compilation, precompiled modules are
    loaded into reconfigurable resources by procedure
    call mechanisms
  • Exploiting information about program branch
    probabilities
  • Promote utilization by dedicating more resources
    the branches which execute more frequently
  • Hardware compiler produces a collection of
    designs, each optimised for a particular branch
    probability, best one is selected at runtime

19
Soft Instruction Processor
  • Two examples of soft instruction processors are
    MizroBlaze and Nios
  • Customisation of resources and instructions is
    supported
  • Time for instruction fetch and decode is reduced,
    each custom instruction replaces several regular
    instructions
  • Additional resources can be assigned to a custom
    instruction to improve the performance

20
Multi-FPGA Compilation
  • Compiler can generate designs using speculative
    and lazy execution to improve the performance
  • A single program is partitioned between host and
    reconfigurable resources

21
Dynamic Instruction Set Computer
22
DISC-Example Code
23
DISC-Example Application
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