Chapter 6 Differential and Multistage Amplifiers

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Chapter 6 Differential and Multistage Amplifiers
Introduction 6.1 The BJT differntial pair 6.2
Small-signal operation of the BJT differential
amplifier 6.3 Other nonideal characteristics of
the differential amplifier 6.4 MOS
diffenrential amplifiers 6.5 Biasing in
intergrated circuits 6.6 The BJT differential
amplifier with active load 6.9 Multistage
amplifiers
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Introduction

• The differential amplifier (pair) configuration
  is the most widely used building block in analog
  IC design.
• BJT differential amplifier is the basis of a
  very-high-speed logic circuit family, called
  emitter-coupled logic (ECL).

Why?
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Reasons
Direct coupling between signal source and
amplifier will easily cause temperature Drift
(zero drift).
What shall we do?
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Advantages

• There are 2 reasons for using differential in
  preference to single-ended amplifiers.
• (1) Differential circuits are much less sensitive
  to noise and interference than single-ended
  circuits.
• (2) It enables us to bias the amplifier and to
  couple amplifier stage without the need of bypass
  and coupling capacitors which are impossible to
  fabricate economically by IC technology.

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6.1 The BJT Differential PairBasic
Operation-1Common-mode input

• The differential pair with a common-mode input
  signal vCM.
• Two transistors are matched.
• Current source with infinite output resistance.
• Current I divide equally between two transistors.
• The difference in voltage between the two
  collector is zero.
• The differential pair rejects the common-mode
  input signal as long as two transistors remain in
  active region.

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Basic Operation-2

• The differential pair with a large differential
  input signal.
• Q1 is on and Q2 is off.
• Current I entirely flows in Q1.

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Basic Operation-3

• The differential pair with a large differential
  input signal of polarity opposite to that in (b).
  
• Q2 is on and Q1 is off.
• Current I entirely flows in Q2.

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Basic Operation-4Difference-mode or Difference
signals

• The differential pair with a small differential
  input signal vi.
• Small signal operation or linear amplifier.
• Assuming the bias current source I to be ideal
  and thus I remains constant with the change in
  vCM.
• Increment in Q1 and decrement in Q2.

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Large-Signal Operation
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Large-Signal Operation

• Nonlinear curves.
• Linear segments.
• Maximum value of input differential voltages
• as a
  small-signal amplifier
• can be
  used as a fast current
• switch
• Enlarge the linear segment by including equal
  resistance Re in series with the emitters.

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Large-Signal Operation
The transfer characteristics of the BJT
differential pair (a) can be linearized by
including resistances in the emitters.
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6.2 Small-signal operation of the BJT
differential amplifier
The currents and voltages in the differential
amplifier when a small differential input signal
vid is applied.
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Small-Signal Operation
A simple technique for determining the signal
currents in a differential amplifier excited by a
differential voltage signal vid dc quantities
are not shown.
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Small-Signal Operation

• A differential amplifier with emitter
  resistances.
• Only signal quantities are shown (in color).

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Input Differential Resistance

• Input differential resistance is finite.
• The resistance seen between the two bases is
  equal to the total resistance in the emitter
  circuit multiplied by (1ß).
• Input differential resistance of differential
  pair with emitter resistors.

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Differential Voltage Gain

• Differential voltage gain
• Output voltage taken single-ended
• Output voltage taken differentially

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Differential Voltage Gain

• Differential voltage gain of the differential
  pair with resistances in the emitter loads
• Output voltage taken single-ended
• Output voltage taken differentially
• The voltage gain is equal to the ratio of the
  total resistance in the collector circuit to the
  total resistance in the emitter circuit.

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Differential Half-Circuit Analysis

• Differential input signals.
• Single voltage at joint emitters is zero.
• The circuit is symmetric.
• Equivalent common-emitter amplifiers in (b).

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Differential Half-Circuit Analysis

• This equivalence applies only for differential
  input signals.
• Either of the two common-emitter amplifiers can
  be used to find the differential gain,
  differential input resistance, frequency
  response, and so on
• Half circuit is biased at I/2.
• The voltage gain(with the output taken
  differentially) is equal to the voltage of half
  circuit.

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Differential Half-Circuit Analysis

• The differential amplifier fed in a single-ended
  manner.
• Signal voltage at the emitter is not zero.
• Almost identical to the symmetric one.

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Common-Mode Gain
The differential amplifier fed by a common-mode
voltage signal vicm.
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Common-Mode Gain
Equivalent half-circuits for common-mode
calculations.
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Common-Mode Gain

• Common-mode voltage gain
• Output voltage taken single-ended
• Output voltage taken differentially

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Common-Mode Rejection Ratio

• Common-mode rejection ratio
• Output voltage taken single-ended
• Output voltage taken differentially
• This is true only when the circuit is symmetric.
• Mismatch on CMRR

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Input Common-Mode Resistance

• Definition of the input common-mode resistance
  Ricm.
• The equivalent common-mode half-circuit.

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Input Common-Mode Resistance

• Input common-mode resistance
• Input common-mode resistance is very large.

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Example 6.1
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Example6.1 (contd)

• Evaluate the following
• The input differential resistance.
• The overall differential voltage gain(neglect the
  effect of ro).
• The worst-case common-mode gain if the two
  collector resistance are accurate within 1.
• The CMRR, in dB.
• The input common-mode resistance(suppose the
  Early voltage is 100V).

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6.3 Other Nonideal characteristic of the
Differential Amplifier

• Input offset voltage Vos
• Ideal differential pair is perfectly matched, but
  practical circuits exhibits
• Mismatches that result in a dc Vo is not zero. Vo
  is the output dc offset
• Voltage. Input offset voltage Vos

• Input bias and offset currents Ios

perfectly matched

• Input Common-Mode Range

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6.4 MOS Differential Amplifiers
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Operation with a Common Mode Input Voltage
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Operation with a Common Mode Input Voltage

• Symmetry circuit.
• Common-mode voltage.
• Current I divides equally between two
  transistors.
• The difference between two drains is zero.
• The differential pair rejects the common-mode
  input signals.

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Operation with a Differential Input Voltage

• The MOS differential pair with a differential
  input signal vid applied.
• With vid positive vGS1 gt vGS2, iD1 gt iD2, and
  vD1 lt vD2 thus (vD2 - vD1) will be positive.
• With vid negative vGS1 lt vGS2, iD1 lt iD2, and
  vD1 gt vD2 thus (vD2 - vD1) will be negative.

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Operation with a Differential Input Voltage

• Differential input voltage.
• Response to the differential input signal.
• The current I can be steered from one MOS to the
  other by varying the differential input voltage
  in the range
• When differential input voltage is very small,
  the differential output voltage is proportional
  to it, and the gain is high.

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Large-Signal Operation

• Transfer characteristic curves
• Normalized plots of the currents in a MOSFET
  differential pair.
• Note that VOV is the overdrive voltage at which
  Q1 and Q2 operate when conducting drain currents
  equal to I/2.

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Large-Signal Operation

• Nonlinear curves.
• Maximum value of input differential voltage.
• When vid 0, two drain currents are equal to
  I/2.
• Linear segment.
• Linearity can be increased by increasing
  overdrive voltage(see next slide).
• Price paid is a reduction in gain(current I is
  kept constant).

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Large-Signal Operation
The linear range of operation of the MOS
differential pair can be extended by operating
the transistor at a higher value of VOV.
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Small-Signal Operation of MOS Differential Pair

• Linear amplifier
• Differential gain
• Common-mode gain
• Common-mode rejection ratio(CMRR)
• Mismatch on CMRR

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Differential Gain

• a common-mode voltage applied to set the dc bias
  voltage at the gates.
• vid applied in a complementary (or balanced)
  manner.

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Differential Gain
Signal voltage at the joint source connection
must be zero.
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Differential Gain
An alternative way of looking at the small-signal
operation of the circuit.
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Differential Gain

• Differential gain
• Output taken single-ended
• Output taken differentially
• Advantages of output signal taken differentially
• Reject common-mode signal
• Increase in gain by a factor of 2(6dB)

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Differential Gain
MOS differential amplifier with ro and RSS taken
into account.
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Differential Gain

• Equivalent circuit for determining the
  differential gain.
• Each of the two halves of the differential
  amplifier circuit is a common-source amplifier,
  known as its differential half-circuit.

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Differential Gain

• Differential gain
• Output taken single-ended
• Output taken differentially

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Common-Mode Gain
The MOS differential amplifier with a common-mode
input signal vicm.
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Common-Mode Gain

• Equivalent circuit for determining the
  common-mode gain (with ro ignored).
• Each half of the circuit is known as the
  common-mode half-circuit.

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Common-Mode Gain

• Common-mode gain
• Output taken single-ended
• Output taken differentially

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Common-Mode Rejection Ratio

• Common-mode rejection ratio(CMRR)
• Output taken single-ended
• Output taken differentially
• This is true only when the circuit is perfectly
  matched.

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Mismatch on CMRR

• Effect of RD mismatch on CMRR
• Effect of gm mismatch on CMRR

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Mismatch on CMRR

• Determine the common-mode gain resulting from a
  mismatch in the gm values of Q1 and Q2.
• Common-mode half circuit is not available due to
  mismatch in circuit.
• The nominal value gm.

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Mismatch on CMRR

• Effect of gm mismatch on CMRR

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Homework

• March 30, 2009
• 6.1 6.18 6.21 6.27
• 6.87

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6.5 Biasing in Integrated Circuits
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Design Philosophy of Integrated Circuits

• Strive to realize as many of the functions
  required as possible using MOS transistors only.
• Large even moderate value resistors are to be
  avoided
• Constant-current sources are readily available.
• Coupling and bypass capacitors are not available
  to be used, except for external use.

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Design Philosophy of Integrated Circuits

• Low-voltage operation can help to reduce power
  dissipation but poses a host of challenges to the
  circuit design.
• Bipolar integrated circuits still offer many
  exciting opportunities to the analog design
  engineer.

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Biasing mechanism for ICs

• BJT Circuits
• The basic BJT current source
• Current-steering
• MOSFET Circuits
• The basic MOSFET current source
• MOS current-steering circuits

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Biasing mechanism for ICs(contd)

• Current-mirror circuits with improved performance
• A bipolar mirror with base-current compensation
• The wilson current mirror
• The current steering circuits
• The widlar current source

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The Basic BJT Current Mirror
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A Simple BJT Current Source.

• Disadvantages
• Increasing Io
• Decreasing Io

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Current Steering
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Current-Mirror Circuits with Improved Performance

• Two performance parameters need to be improved
• The accuracy of the current transfer ratio of the
  mirror.
• The output resistance of the current source.

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Current Mirror with Base-Current Compensation
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The Wilson Bipolar Current Mirror
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The Widlar Current Source
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The advantages of Widlar Current Source

• Example6.2 p518
• Widlar circuit allows the generation of a small
  constant current using relatively small
  resistors( saving in chip area ).
• Another important characteristic of the widlar
  current source is that its output resistance is
  high.

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The Basic MOSFET Current Source
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MOS Current-Steering Circuits
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The Wilson MOS Current Mirror
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6.6 The Differential Amplifier with Active Load

• Replace resistance RD with a constant current
  source results in a much high voltage gain as
  well as saving in chip area.
• Convert the output from differential to
  single-ended.

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The Bipolar Differential Pair with Active Load
Quiescent analysis if the circuit Is perfectly
matched, no output Current flows through the
output Terminal.
Active-loaded bipolar differential pair.
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Determine the Transconductance
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Differential Gain

• The differential gain is determined as GmRo
• When
• Input differential resistance

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Common-Mode Gain and CMRR

• Common-mode gain
• CMRR

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Differential-to-Single-Ended Conversion
Drawback Lose a factor of 2(or 6 dB)
A simple but inefficient approach for
differential to single-ended conversion.
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The Active-Loaded MOS Differential Pair
The active-loaded MOS differential pair.
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The Active-Loaded MOS Differential Pair
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The Active-Loaded MOS Differential Pair
The circuit with a differential input signal
applied, neglecting the ro of all transistors.
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Differential Gain of the Active-Loaded MOS Pair

• The output resistance ro plays a significant role
  in the operation of active-loaded amplifier.
• Asymmetric circuit.
• Half-circuit is not available.
• The gain will be determined as GmRo

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Short-Circuit Transconductance
Determining the short-circuit transconductance Gm
io/vid
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Short-Circuit Transconductance
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Output Resistance
Circuit for determining Ro. The circled numbers
indicate the order of the analysis steps.
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Output Resistance

• Circuit for determining Ro.
• The circled numbers indicate the order of the
  analysis steps.

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Differential Gain

• The differential gain is determined as GmRo
• When

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Common-Mode Gain and CMRR

• Analysis of the active-loaded MOS differential
  amplifier to determine its common-mode gain.
• Power supplies eliminated.
• Rss is the output resistance of the current
  source.

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Common-Mode Gain and CMRR

• Asymmetric circuit.
• Each of the two transistors as a CS configuration
  with a large source degeneration resistance 2Rss.
• Common-mode gain
• CMRR

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Comparison with MOS circuits

1. The MOS mirror does not suffer from the
   finite-ßeffect.
2. In the BJT mirror and current source, the output
   voltage can be within VCEsat the corresponding
   value in MOS circuit is VGS-VtgtVCEsat, where
   power-supply voltages are being steadily reduced.
3. The current transfer ratio in the BJT mirror is
   determined by the relative areas of the
   transistors, whereas in a MOS mirror it is
   determined by the relative (W/L) ratio.
4. Both of mirror circuit have an output resistance
   of roVA/I, however, VA is usually lower for MOS
   devices.

Note The fifth edition P550-552
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Homework

• April 8th, 2009
• 6.45 D6.60

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6.7 Multistage Amplifiers
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Multistage Amplifier
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Multistage Amplifier

• The first stage(input stage) is differential-in,
  differential-out and consists of Q1 and Q2.
• The second stage is differential-in,
  single-ended-out amplifier which consists of Q3
  and Q4.
• The third stage is CE amplifier which consists of
  pnp transistor Q7 to shifting the dc level.
• The last stage is the emitter follower.
• Biasing stage.

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Multistage Amplifier
Equivalent circuit for calculating the gain of
the input stage of the example. Input
differential resistance Gain of first stage
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Multistage Amplifier
Equivalent circuit for calculating the gain of
the second stage of the example. Gain of second
stage
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Multistage Amplifier
Equivalent circuit for calculating the gain of
the third stage of the example. Gain of third
stage
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Multistage Amplifier
Equivalent circuit for calculating the gain of
the output stage of the example. Gain of output
stage Output resistance
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Two-Stage CMOS Op-Amp Configuration
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Homework
April 8th, 2008 6.87 6.121