MAPS with pixel level sparsified readout: from standard CMOS to vertical integration

1
MAPS with pixel level sparsified readout from
standard CMOS to vertical integration
L. Gaionia,c, A. Manazzaa, M. Manghisonib,c, L.
Rattia,c, V. Reb,c, G. Traversib,c
aUniversità degli Studi di Pavia bUniversità
degli Studi di Bergamo cINFN Pavia
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Outline

• Motivation
• CMOS Monolithic Active Pixel Sensors (MAPS) for
  tracking in future high energy physics
  experiments
• Deep n-well (DNW) MAPS features
• DNW MAPS in planar technology
• DNW MAPS in 3D technology
• Analog and digital front-end
• Design consideration
• Readout architecture
• Detection efficiency
• Conclusion

VERTEX 2009 (18th workshop), 13-18 September
2009, VELUWE, the Netherlands L. Gaioni,
3D DNW MAPS
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Motivation

• Future experiments at next generation colliders
  like ILC and Super B-Factory require fast, highly
  granular, low mass detectors
• CMOS MAPS features
• minimal readout electronics ? small pitch, high
  spatial resolution
• sensing element shares the same substrate with
  the readout electronics
• substrate thickness can be reduced to a few tens
  of microns
• fast readout may be a problem
• Because of the large amount of data produced in
  the readout of large matrices, an innovative
  solution of MAPS, based on triple well
  structures, was proposed ? Deep N-well MAPS (DNW
  MAPS) allow designers to implement more complex,
  fast readout circuits
• capabilities for pixel level sparsification and
  time stamping
• fully CMOS architecture
• relatively small area for the digital front-end
  (FE)
• detection efficiency maybe degraded
• Vertical integration may lead to the full
  compliance with the experiment specifications ?
  3D DNW MAPS

VERTEX 2009 (18th workshop), 13-18 September
2009, VELUWE, the Netherlands L. Gaioni,
3D DNW MAPS
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CMOS MAPS

• Have been proposed as suitable candidates for
  charged particle trackers at the next generation
  colliders
• Several features make them appealing for such
  applications
• sensor and readout electronics share the same
  substrate ? low material budget
• low power consumption and fabrication costs

• Minority carriers released along the track move
  by thermal diffusion in the undepleted epitaxial
  layer
• N-well/P-epitaxial diode acts as collecting
  element
• Sensor capacitance (CD) used to convert the
  collected charge to a voltage signal ? small
  electrode
• Simple in-pixel readout architecture ? sequential
  readout
• See next talk (C. HU-GUO) for state of the art of
  CMOS MAPS MIMOSA

VERTEX 2009 (18th workshop), 13-18 September
2009, VELUWE, the Netherlands L. Gaioni,
3D DNW MAPS
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Deep N-well MAPS

• Deep N-well provided by triple-well CMOS
  processes is used to shield nMOSFETs from
  substrate noise
• This feature was exploited in the realization of
  a new kind of CMOS pixels ? DNW MAPS devices

• The DNW acts as collecting element for the charge
  released in the substrate
• A readout chain for capacitive detectors is used
  for Q-V conversion ? gain decoupled from
  electrode capacitance
• NMOS transistor of the analog section hosted in
  the deep N-well
• Sensor can be extended to cover a large area of
  the pixel cell ? PMOS device can be included in
  the front-end design
• Fully CMOS design ? high functional density
• Fill factor DNW/total n-well area

VERTEX 2009 (18th workshop), 13-18 September
2009, VELUWE, the Netherlands L. Gaioni,
3D DNW MAPS
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DNW MAPS analog front-end

• Shaperless version of an optimum readout chain
  for capacitive detectors
• The analog processor includes a charge sensitive
  amplifier and a threshold discriminator ? binary
  readout

• SDR0 prototype designed in a 130 nm technology
  (25 µm pitch)

VERTEX 2009 (18th workshop), 13-18 September
2009, VELUWE, the Netherlands L. Gaioni,
3D DNW MAPS
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SDR0, a DNW MAPS for the ILC vertex

• Digital front-end enables single hit-storage and
  5-bit time stamping, and includes sparsification
  blocks (token passing scheme)
• Sensor operation is based on the ILC beam
  structure
• Detection phase corresponding to bunch train
  period
• Readout phase corresponding to intertrain
  period

• Sparsification logic
• Token passing core
• Hit-latch
• Bus control FF
• Nand gate

• Preamplifier
• Discriminator

DNW sensor
Time stamp register
25 mm
VERTEX 2009 (18th workshop), 13-18 September
2009, VELUWE, the Netherlands L. Gaioni,
3D DNW MAPS
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SDR0 features and experimental results

• W/L input device 22/0.25
• Power consumption 5 µW
• Equivalent noise charge 50 e- _at_ CD 100 fF
• Threshold dispersion 50 e- (main contributions
  from preamplifier input device and NMOS and PMOS
  pair in the discriminator)
• Charge sensitivity 650 mV/fC
• Power Down option for power saving

Matrix response to infrared laser
Digital readout is working fine
Test with 55Fe
VERTEX 2009 (18th workshop), 13-18 September
2009, VELUWE, the Netherlands L. Gaioni,
3D DNW MAPS
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DNW MAPS the APSEL series

• ASPEL series first generation DNW MAPS with
  on-pixel data sparsification and time stamping,
  continuous readout, tested in a beam for the
  first time in September 2008
• resolution lt 18 mm (50 mm x 50 mm pixels)
• efficiency plateau close to 90
• sensors, readout chips, DAQ systems and AM boards
  are working fine

• Two major flaws affect the overall performance of
  the DNW MAPS
• detection efficiency may be inadequate fully
  CMOS electronics requires a non negligible amount
  of n-well area for the integration of PMOS
  devices
• single-hit detection
• Extensive RD on 2D DNW MAPS ongoing (layout
  optimization)
• 3D integration processes, the technology leap

VERTEX 2009 (18th workshop), 13-18 September
2009, VELUWE, the Netherlands L. Gaioni,
3D DNW MAPS
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3D Integrated Circuit

• In wafer-level, 3D processes, multiple layers of
  planar devices are stacked and interconnected
  using through silicon vias (TSV)

• Key technologies needed for 3D
• alignment and Mechanical/electrical bonding
  between layers
• wafer thinning (below 50 mm)
• Realization of electrically isolated connections
  through the silicon substrate (TSV formation)
• Advantages
• Reduced chip size
• Reduced parasitics
• Reduced power
• Fabrication process optimized by tier function
• Tezzaron Semiconductor technology can be used to
  vertically integrate two layers specifically
  processed by Chartered Semiconductor (130 nm
  CMOS, 1 poly, 6 metal layers, 2 top metals, dual
  gate, N- and PMOS available with different Vth)

VERTEX 2009 (18th workshop), 13-18 September
2009, VELUWE, the Netherlands L. Gaioni,
3D DNW MAPS
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Tezzaron/Chartered run

• In the last few months several Italian teams
  (from INFN Bologna, Pavia, Perugia, Pisa and Roma
  III and Universities of Bergamo, Pavia, Perugia
  and Pisa), together with Fermilab and a number of
  French (In2P3), Polish and German groups, have
  been working within the 3DIC Consortium on a MPW
  run in the Tezzaron/Chartered 3D IC fabrication
  process
• The 3D IC Consortium
• includes FNAL and several Italian and French
  Institutions (also Bonn and AGH Universities, see
  http//3dic.fnal.gov) aiming to work together on
  a MPW run using the Tezzaron 3D IC fabrication
  process
• the collaborating institutions are willing to
  share information on design tools and design rule
  implementation, cell libraries, circuit blocks
  (besides costs)
• as far as the Italian contribution is concerned,
  this first submission, funded in the frame of the
  P-ILC experiment, will include MAPS sensors
  mainly for applications to the ILC, but also some
  APSEL structures

VERTEX 2009 (18th workshop), 13-18 September
2009, VELUWE, the Netherlands L. Gaioni,
3D DNW MAPS
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DNW MAPS from 2D to 3D

• Tier 1 includes collecting electrode (deep
  N-well/P-substrate junction), analog front-end
  and discriminator
• Tier 2 includes digital front-end (2 latches for
  hit storage, pixel-level digital blocks for
  sparsification, 2 time stamp registers, kill
  mask) and digital back-end (X and Y registers,
  time stamp line drivers, serializer)
• Separation of analog and digital sections ? lower
  cross-talk
• A 3D DNW MAPS for the ILC vtx ? the SDR1 chip

VERTEX 2009 (18th workshop), 13-18 September
2009, VELUWE, the Netherlands L. Gaioni,
3D DNW MAPS
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SDR1 analog front-end and discriminator

• Limited use of PMOS devices in the sensor layer

• Preamplifier PMOS devices are kept in the analog
  layer (TIER 1), whereas large area PMOS from
  discriminator are integrated in the digital layer
  (TIER 2)

VERTEX 2009 (18th workshop), 13-18 September
2009, VELUWE, the Netherlands L. Gaioni,
3D DNW MAPS
14
Analog FE features and simulation results

• W/L input device 20/0.18
• Power consumption 5 µW
• Equivalent noise charge 35 e- _at_ CD 200 fF
• Threshold dispersion 36 e- (main contributions
  from preamplifier input device and NMOS and PMOS
  pair in the discriminator)
• Charge sensitivity 800 mV/fC
• Power Down option for power saving

Linearity
Preamplifier response
VERTEX 2009 (18th workshop), 13-18 September
2009, VELUWE, the Netherlands L. Gaioni,
3D DNW MAPS
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Geometrical features of the DNW electrode

• Placing most of the PMOS on the digital layer may
  reduce the area covered by competitive electrodes
  ? better efficiency
• The DNW covers about 35 of the cell area in the
  SDR0 chip, more than 50 in its 3D release

DNW (collecting electrode)
20 mm
NW
SDR1 cell (bottom tier)
SDR0 cell
VERTEX 2009 (18th workshop), 13-18 September
2009, VELUWE, the Netherlands L. Gaioni,
3D DNW MAPS
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Sensor detection efficiency and cluster size

• Monte Carlo simulations on matrices of 3x3 DNW
  MAPS featuring the layout of the SDR0 and SDR1
  sensors (10000 experiments, 80 µm thick
  substrate)

VERTEX 2009 (18th workshop), 13-18 September
2009, VELUWE, the Netherlands L. Gaioni,
3D DNW MAPS
17
Digital front-end

• Increased functional density with respect to SDR0
  chip
• Each pixel is able to keep information about two
  hits with the relevant 5-bit time stamps

VERTEX 2009 (18th workshop), 13-18 September
2009, VELUWE, the Netherlands L. Gaioni,
3D DNW MAPS
18
Digital front-end

• During the bunch train period, the SR FF (FFSRK)
  is set when the pixel is hit the first time and
  the relevant time stamp register gets frozen
• Upon a second hit, the D FF (FFDR) is set and the
  relevant time stamp register gets frozen

VERTEX 2009 (18th workshop), 13-18 September
2009, VELUWE, the Netherlands L. Gaioni,
3D DNW MAPS
19
Token passing readout architecture
Suggested by FNAL IC design group, first
implemented in the VIP chip
ReadOutCLK
DataOut
MUX
8
5
X256
X2
X1
TSBUF
TSBUF
TSBUF
FirstTokenIn
gXGetX gYGetY TSTStampOut tkiTokenIn tkoToken
Out
8
Y1
Y2
Time stamp counter
Y240
LastTokenOut
VERTEX 2009 (18th workshop), 13-18 September
2009, VELUWE, the Netherlands L. Gaioni,
3D DNW MAPS
20
Cell layout
Inter-tier connections
Inter-tier connections
DNW sensor
Analog section and discriminator NMOS
Digital section and discriminator PMOS
N-well
VERTEX 2009 (18th workshop), 13-18 September
2009, VELUWE, the Netherlands L. Gaioni,
3D DNW MAPS
21
Conclusion

• Vertical integration processes are very promising
  for the fabrication of MAPS for the next
  generation colliders
• 3D DNW MAPS have the following advantages
  compared with the 2D devices
• better collection efficiency due to the reduced
  area covered by competitive n-wells in the analog
  tier
• reduction of cross-talk between analog/sensor and
  digital blocks
• improved functional density
• Experimental characterization of the fisrt 3D
  prototypes is foreseen in November
• Next step 3D front-end chip vertically
  integrated to a high resistivity
  fully-depleted sensor

VERTEX 2009 (18th workshop), 13-18 September
2009, VELUWE, the Netherlands L. Gaioni,
3D DNW MAPS
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Backup
VERTEX 2009 (18th workshop), 13-18 September
2009, VELUWE, the Netherlands L. Gaioni,
3D DNW MAPS
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DNW MAPS and vertical integration

• Vertical integration between two layers of 130nm
  CMOS chips
• The first layer may include a DNW MAPS device
  with analog readout, with digital readout
  circuits in the second layer
• Overcome limitations typically associated with
  conventional and DNW CMOS MAPS
• Reduced pixel pitch
• 100 fill factor (few or no PMOS in the sensor
  layer)
• Better S/N vs power dissipation performance
  (smaller sensor capacitance)
• Reduction of digital-to-analog interferences
• Increased pixel functionalities (removal of
  layout constraints allow for an improved readout
  architecture, analog information,.)

VERTEX 2009 (18th workshop), 13-18 September
2009, VELUWE, the Netherlands L. Gaioni,
3D DNW MAPS
24
Digital FE detection efficiency

• Detection efficieny turns out to be increased
  thanks to the increased functional density in the
  digital FE
• Curves obtained by taking into account the
  average cluster size (1.13 for SDR0, 2.35 for
  SDR1) at a discriminator threshold of 300 e-
• Detection efficiency in the SDR1 DFE is larger
  than 99 for a hit occupancy of
  0.15/particles/BCO/mm2

VERTEX 2009 (18th workshop), 13-18 September
2009, VELUWE, the Netherlands L. Gaioni,
3D DNW MAPS