Agenda

1
Agenda

• Introduction
• Overview of RF Design Process
• Case Study RF Front-End
• Low-Noise Amplifier (LNA)
• Duplexer
• Power Amplifier
• Measurement for Design
• Passive Device Characterization
• Active Device Parameter Extraction
• Summary

2
Power Amp Design

• 1.88 GHz PCS-Band Amplifier
• Gain gt 24 dB
• 1-dB-compression gt 25 dBm
• Psat gt 27 dBm
• Main challenge designing for maximum power
  output
• During brainstorm process, decided
• two stages needed to get desired gain
• stage one
• silicon transistor
• passive bias
• stage two
• power FET
• active bias

power stage
driver stage
3
Bias Considerations - Active vs. Passive

• passive - simpler, less space, cheaper but not as
  well controlled
• active - extra circuitry, but more repeatable
• hint watch out for over-biasing junctions (FET
  gate-bias example)

changed to -6V to prevent gate over-voltage
condition
4
Designing the Output Stage for Maximum Output
Power

• output impedance varies as function of output
  power
• ideal impedance exists for maximum output power
• two technique provides information for
  output-stage matching
• load-pull technique
• load-line analysis

Low power
High power
5
Load-Pull Technique

• vary magnitude and phase of load presented to
  circuit
• power output is measured at each impedance point
• can use behavioral model (based on measurements)

Output impedance and power measurement system
Input impedance and power measurement system
X
X
X
X
Input Tuner
Output Tuner
Constant output power contours versus output load
impedance (input power constant)
Can be very expensive and time-intensive
6
Load-Line Analysis

• determines resistance that gives highest power
• current source of FET needs to be presented with
  this load
• should give same output match as load-pull
  technique

7
Matching to FET Output
Output match of FET chip

• need to have accurate physical model of device
• parasitics must be included in matching circuit
• include FET and package parasitics
• assume simple parallel-output capacitance for FET
• can determine Cp from chip model
• use mirror-matching technique

M1
external output matching circuit
Package model
Ouput capacitance of FET
Load resistor determined from load-line analysis
match to 50 ohms here
Id Vgate x gm

Vgate
Co
-
Co y / (2pf 50) 1.02 pf
8
Load-Pull Simulation
- 6 dB contour - 5 dB contour - 4 dB contour -
3 dB contour - 2 dB contour
Pmax ( 32.4 j 35.7 )
- 1 dB contour
Simpler, Faster, and Far less expensive
our designed impedance
( 42.15 j 23.45 )
9
Using data from the load-pull simulation to
design a matching network

• No need to model parasitics of FET or package
• Use mirror-matching technique
• Easier and faster

Conjugate match of load impedance
external output matching circuit
- j 23.45
42.15 ohms
match to 50 ohms here
10
Measured Performance of First Prototype
CH1
S

log MAG
10 dB/
REF 30 dB
21


1_ 1.641 GHz 30.39 dB
PRm


2_ 1.880 GHz 17.584 dB
3
Cor
3_ 651.419 MHz 40.93 dB
Avg
measured
0
simulated (entire amp)
1
Hld


2
simulated (preamp only)


START 100.000 000 MHz
STOP 3 000.000 000 MHz
11
Modifying Tips
First, verify there are no errors in the
fabrication or measurement of the prototype.
Why modify the circuit design file to match the
prototype?
Because a prototype is a very useful tool for
improving the accuracy of the circuit design
file gives good assurance that design changes
will indeed improve design
Can start by,
- accounting for fringing effects or
discontinuities - removing transistor and
measuring only bias components - connecting
ground vias directly to the main transmission
line
12
Modify the circuit design file
13
Importance of accurate measurements
Desired reference plane
(A) (B) (C) (D)
Reference plane, set by test fixture calibration
Reference plane of capacitors measured
s-parameter
Desired reference plane of capacitors measured
s-parameter
test fixture
(additional transmission line lengths, 20 mils
on either side)
Modified s-parameter model of capacitor
14
Design Refinement
driver stage
power stage
s22
s11
2 gain stages, oscillation can be caused by ..
driver stage .. power stage .. both stages ----gt
Need to separate each stage and examine
15
Driver Stage
Gain
Stability Circles
16
Power Stage Input Output Match
Potentially Unstable
17
Schematic of New Power Stage
trap
feedback loop
18
Completed amplifiers s11 and s22 responses with
duplexer filter connected
Analysis using filter s-parameter file, obtained
over a narrow frequency band
Analysis using filter s-parameter file, obtained
over an appropriately wide frequency band
19
Working Power Amplifier !
Simulated
Measured
20
Input and Output Match
S22
s22
2
s11
21
Characterizing Nonlinear Behavior

• Power amplifiers require additional measurements
  to characterize nonlinear behavior
• power sweeps (using network analyzer)
• gain compression
• AM to PM conversion
• single-tone harmonic
• second harmonic
• third harmonic
• multi-tone intermodulation
• third-order intercept using two tones
• high-order intermodulation using many carriers
• digital modulation
• adjacent-channel power

22
Power Sweep - Compression
Saturated output power
Output Power (dBm)
Compression region
Linear region (slope small-signal gain)
Input Power (dBm)
23
Measured Gain Compression

• 1 dB compression
• input power resulting in
• 1 dB drop in gain
• ratioed measurement
• output power available (non-ratioed measurement)
• use power-meter calibration for best accuracy

1dB Compression Results Input power 3.7 dBm
Output power 27.633 dBm
Gain,1dB 23.933 dB
24
Simulated Gain Compression
25
Amplifier Specification Sheet
26
Digital Modulation Review Cellular Access Methods
27
Digital Modulation Review signal characteristics
to modulate
Amplitude
Frequency
Phase
Both Amplitude and Phase
28
Digital Modulation Review Polar Display
Magnitude Phase Represented Together
0 deg

• Magnitude is an absolute value
• Phase is relative to a reference signal

29

• Digital Modulation Review
• Signal Changes or Modifications

Mag
Phase
0 deg
0 deg
Magnitude Change
Phase Change
0 deg
Both Change
30
Digital Modulation Review Polar vs. I/Q Format
0 deg
Project signal to I and Q axes
Polar to Rectangular Conversion
31

• Digital Modulation Review
• Binary Phase Shift Keying (BPSK)
• I/Q Diagram

32

• Digital Modulation Review
• Quadrature Phase Shift Keying (QPSK)
• IQ Diagram

Q
00
01
I
10
11
33
Digital Modulation Review CDMA Modulation Formats
34
Agenda

• Power amplifier
• Design
• CDMA
• test description
• simulations
• measurements
• GSM
• test description
• simulation
• measurements

35
CDMA Tests

• Channel Power
• Adjacent Channel Power Ratio
• (ACPR)
• Modulation Quality

36
CDMA Tests
Channel Power is band limited to 1.23 MHz
37
CDMA Tests
ACPR compares in-channel power to
out-of-channel power
Base Station Spec lt-45 dBc _at_ 885 KHz
38
HP E4433B ESG Generator
CDMA Tests
Whats CCDF?
Assures adequate test signal for ACPR
39
CDMA Tests
Modulation Quality (EVM Rho)
40
Whats EVM?

Q
Magnitude Error (I/Q error mag)

Error Vector Magnitude (EVM)
Test
Signal
f
Ideal (Reference) Signal
Phase Error (I/Q error phase)
I
EVM is the RMS value of the error vector.
41
Whats Rho?
If data is spread and de-spread perfectly,
Rho1 Base Station Spec gt.912, Mobile gt.944
42
CDMA Tests
Simulation Setup
HP Advanced Design System
43
CDMA Tests
Measurement set-up
HP E4406A VSA Analyzer
HP E4433B ESG Generator
44
CDMA Tests
Channel Power and ACPR
Simulation Measured
Pwr 11.2 dBm Pwr 10.8 dBm ACPR lt -70
dBc ACPR lt -70 dBc
45
CDMA Tests
Channel Power and ACPR in Saturation
Simulation Measured
Pwr 23.7 dBm Pwr 23.2 dBm ACPR lt -47
dBc ACPR lt -47 dBc
46
CDMA Tests
EVM and Rho - No Saturation
Simulation Measured
EVM .7 EVM 1.5 Rho .999
Rho .999
47
CDMA Tests
EVM and Rho In Saturation
Simulation Measured
EVM 8 EVM 5 Rho .994 Rho
.997
48
FSK Modulation Review
49
GSM Amplifier Specification Sheet
50
GSM Tests

• Power Vs. Time
• Output RF Spectrum
• Phase and Freq.
• Error

51
GSM Tests
Power vs. Time Measurements Verify Flatness and
Timing of the RF Burst.
52
GSM Tests
Output RF Spectrum Measurements Examine
Adjacent Channel Interference
53
GSM Tests
Phase and Frequency Error Determine the Quality
of Modulation
54
GSM Tests
Simulation Setup
HP Advanced Design System
55
GSM Tests
Measurement Setup
HP E4406A VSA Analyzer
HP E4433B ESG Generator
56
GSM Tests
Power versus Time
Simulation Measured
57
GSM Tests
Output RF Spectrum
Simulation Measured
58
GSM Tests
Phase and Frequency Error
Simulation Measured
Phase Error lt 1deg Phase Error lt 1deg Freq.
Error lt 5 Hz Freq. Error lt 5 Hz
59
3G
1G
2G

• Wider Bandwidths
• More Capacity
• Higher Data Rates
• W-CDMA Proposed

60
HP W-CDMA Solutions
61
References and More Information

• CDMA - www.cdg.org
• GSM - www.gsmdata.com
• W-CDMA - www.hp.com