Dynamic Logic

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Dynamic Logic

• Dynamic Circuits will be introduced and their
  performance in terms of power, area, delay,
  energy and AT2 will be reviewed.
• We will review the following logic families
• Domino logic
• P-E logic
• NORA logic
• 2-phase logic
• Multiple O/P domino logic
• Cascode logic

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A brief introduction to Dynamic logic

• Dynamic logic
• Steady-State Behavior of Dynamic Logic
• Performance of Dynamic Logic
• Noise Considerations in Dynamic Design

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Dynamic Latch Charge Leakage

• Stored charge leaks away due to reverse-bias
  current.
• Stored value is good for about 1 ms.
• Value must be rewritten to be valid.
• If not loaded every cycle, otherwise it must be
  ensured that the latch is loaded often enough to
  keep data valid.

X
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Dynamic Latch-Operation

• Uses complementary transmission gate to ensure
  that storage node is always strongly driven.
• Latch is transparent when transmission gate is
  closed.
• Storage capacitance comes primarily from
  transmission gate diffusion capacitance and
  inverter gate capacitance.
• ? 0 transmission gate is off, inverter output
  is determined by storage node.
• ? 1 transmission gate is on, inverter output
  follows D input.
• Setup and hold times determined by transmission
  gatemust ensure that value stored on
  transmission gate is solid.

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Dynamic Combinational Logic
Precharge/ Evaluate Networks

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Example of Dynamic Circuit
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General ConceptPrecharge and Evaluation
Example of nmos block For OUTPUT (A.B C)
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Charge and discharge
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Overcoming the charge leakage and the charge
sharing
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Example continue
V
DD
M
f
p
N 1 Transistors
Out
Ratioless
No Static Power Consumption
A
Noise Margins small (NM
)
L
C
Requires Clock
B
f
M
e
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Charge Leakage
Solution Make CL small by reducing the drain Cd
and Gate Cg capacitance small.
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Charge Sharing

• To Reduce Charge Sharing
• Increase Cout
• Reduce Cg of input transistors
• Use feedback transistor at the output

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Clock Feed through
Solution Make contacts to the substrate to Gnd,
Vdd to take away the injected electrons
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Cascading Dynamic Logic
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Transient Response
6.0
f
V
out
4.0
)
PRECHARGE
t
EVALUATION
l
o
V
(

t
u
o
V
2.0
0.0
0.00e00
2.00e-09
4.00e-09
6.00e-09
t (nsec)
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4 Input NAND
VDD
Out
In1
In2
In3
In4
f
GND
Prentice Hall/Rabaey
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Dynamic Flip-Flop
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P-E logic

• Instead of using a static invert to ensure that 0
  to 1 transitions occur during precharge, we can
  exploit the duality between ?n- block and
  ?p-block . The precharge output value of ?n-
  block equals 1, which is the correct value for
  the input of a ?p-block during precharge. All
  PMOS transistors of the Pull-Up Network (PUN) are
  turned off, so, an erroneous discharge at the on
  set of the evaluation phase is prevented. In a
  similar way, an ?n- block can follow a ?p-block
  without any problem, as the precharge value of
  inputs equals 0. To make the evaluation and
  precharge times of the ?p and ?n-block coincide,
  one has to clock the ?p-block with an inverted
  clock ?p.

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PE Logic
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Domino logic

• A Domino logic module consists of a ?n block
  followed by a static inverter. This ensures that
  all inputs to the next logic block are set to 0
  after the precharge periods. Hence, the only
  possible transition during the evaluation period
  is 0 to 1 transition, so that formulated rule is
  obeyed.

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The block of Domino logic
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One Bit full Adder-Domino
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Simulation Results
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2-Phase Logic

• We can use two-phase clock to control logic
  transition similar to PE. A single clock (phi1 or
  phi2) is used to precharge and evaluate the logic
  block. The succeeding stage is operated on the
  opposite clock phase. A latch is needed between
  two stages.

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2-Phase logic
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2-Phase Domino logic
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Multiple O/P Domino Logic

• The main concept behind MODL is the utilization
  of sub-functions available in the logic tree of
  domino gates, thus saving replication of
  circuitry. The additional ouputs are obtained by
  adding precharge devices and static inverters at
  the corresponding intermediate nodes of the logic
  tree.

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Multiple output Domino
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MODL 4-bit Carry Block
C 1 G 1 P 1 C 0 C 2 G 2 P 2 G 1 P 2
P 1 C o C 3 G 3 P 3 G 2 P 3 P 2 G 1 P 3 P
2 P 1 C 0 C 4 G 4 P 4 G 3 P 4 P 3 G 2 P 4
P 3 P 2 G 1 P 4 P 3 P 2 P 1 C 0
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CMOS2 Logic
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CMOS2 and Domino Logic
F
CLK
CLK
D
N BLOCK
A
F
A
CLK
CLK
B
C
A
CLK
B C D
B C D
CMOS2 Latch/INV
Domino Logic
Latch/INV
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Example of CMOS2 Logic
F AB BC D, F (AB BC D)
(A B)(B C)D D(AC B)
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NORA Logic

• Combining C2MOS pipeline register and P-E CMOS
  dynamic logic function block, we get NORA-CMOS
  (mean NO-Race). The method is suitable for the
  implementation of pipelined datapaths.

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The block of NORA logic
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Cascode Logic

• Further refinement leads to a clocked version of
  the CVSL gate. This is really just two Domino
  gates operating on the true and complement inputs
  with a minimized logic tree. The advantage of
  this style of logic over domino logic is the
  ability to generate any logic expression, making
  it a complete logic family. This is achieved at
  the expense of the extra routing, active area,
  and complexity associated with dealing-rail
  logic.

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CASCOD Logic
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A clocked version of the CVSL gate
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The block of 8-bit DRCA using the Cascode logic
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Comparison of 8-bit Adders Designed with Dynamic
Logic

• Seven circuits using six dynamic logic functions
  are designed and simulated. The performance in
  terms of power, area, delay, energy and AT2 are
  compared.

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Dynamic Logic Adders that are designed and
compared

• Domino logic 8-bit Adder
• P-E logic 8-bit Adder
• NORA logic 8-bit Adder
• 2-Phase Logic 8-bit Adder
• Multiple O/P Domino Logic 8-bit Adder
• Cascode Logic 8-bit Adder

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Power
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Area
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Delay
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DP
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AT2
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Conclusion

• Domino Logic It has minimum area and number of
  transistors. The power consumption is low, and
  the delay is the longest. The DP and AT2 are
  average. If the design goal is minimum area and
  speed is a secondary concern the Domino logic is
  the best structure for Ripple Carry Adder.

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Conclusion.

• P-E Logic has a small area and the minimum
  number of transistors. The power consumption is
  low, and the delay is short. It has the lower DP
  and AT2 for Ripple Carry Adder. If the logic has
  no inherent race problem, it will be the best
  choice for Ripple Carry Adder.

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Conclusion.

• P-E (race-free) Logic In order to avoid the race
  condition of P-E Logic, the P-E (race-free) Logic
  is introduced. It has a small area and average of
  number of the transistors. The area and number of
  transistors is larger than P-E logic. The power
  consumption is average. The delay is shortest.
  It has lower DP and AT2 for Ripple Carry Adder.
  For synthesis, it is the best choice for Ripple
  Carry Adder.

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Conclusion.

• NORA Logic The power consumption is higher. The
  area is small, and using a few transistors except
  Domino logic. The delay is longer. The DP is high
  and AT2 are average.

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Conclusion.

• 2-Phase Logic The area is larger and the number
  of transistors is more than others except Cascode
  logic. The delay is longer. The power
  consumption, DP and AT2 are extremely high. Try
  to avoid this logic structure for designing
  Ripple Carry Adder.

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2-phase domino logic
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Dynamic Circuits Advantages Disadvantages

• Advantages
• Circuits occupy less area the static circuits
• Operate at higher speed than static CMOS
• Noise sensitive
• Drawbacks
• Affected by charge sharing and charge re-
  distribution
• Always require clocks
• Cannot operate at low frequency
• Design is not straight forward

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Race Condition of PE device