CPLDs and FPGAs: Technology and Design Features

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Lesson 1

• CPLDs and FPGAs Technology and Design Features

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Topics

• Fundamental Concepts
• CPLDs vs FPGAs
• CPLD Architectures
• FPGA Architectures
• Design Methods for FPGA-based Systems
• Intellectual Property
• System-on-chip
• Reconfigurable Computing
• Future FPGA Developments

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1. Fundamental Concepts

• What are CPLDs and FPGAs?
• Complex Programmable Logic Devices (CPLDs) and
  Field Gate Arrays (FPGAs) are digital integrated
  circuits (ICs) that contain configurable
  (programmable) blocks of logic along with
  configurable interconnects between these blocks.
• Design engineers can configure (program) such
  devices to perform a tremendous variety of tasks

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Classification of Digital ICs
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They thing about CPLDs and FPGAs The thing that
really distinguish an FPGA or a CPLD from an ASIC
is the programmable feature.
Let us consider a simple programmable function
In order to make our function more interesting,
we need some mechanism that allows us to
establish one or more of the potential links.
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Fusible link technology
These fuses are similar in to household fuses.
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Programmed fusible links
Devices based on fusible-link technologies are
said to be one-time programmable, or OTP. FPGAs
dont use them.
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Antifuse Technologies

• Antifuse links are an alternative to fuse links.
• An antifuse link is programmable by applying a
  voltage across it.
• An antifuse is given as follows

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Other Technologies

• EPROM
• EEPROM
• FLASH
• SRAM

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2. CPLDs vs. FPGAs

• CPLD architecture
• Small number of PLDs on a single chip
• Programmable interconnect between PLDs

PLDs PALs, PLAs,or GALs
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• FPGA architecture
• Much larger number of smaller programmable logic
  blocks.
• Embedded in a sea of lots and lots of
  programmable interconnect.

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3. CPLD Architectures

• Identical individual PLD blocks (Xilinx FBs)
  replicated in different family members.
• Different number of PLD blocks
• Different number of I/O pins
• Many CPLDs have fewer I/O pins than macrocells
• Buried Macrocells -- provide needed logic terms
  internally but these outputs are not connected
  externally.
• IC package size dictates of I/O pins but not
  the total of macrocells.
• Typical CPLD families have devices with differing
  resources in the same IC package.

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Xilinx CPLDs

• Notice overlap in resource availability in a
  particular package.

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Xilinx 9500-family CPLD architecture
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9500-family function blocks (FBs)

• 18 macrocells per FB
• 36 inputs per FB (partitioning challenge, but
  also reason for relatively compact size of FBs)
• Macrocell outputs can go to I/O cells or back
  into switch matrix to be routed to this or other
  FBs.

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9500-series macrocell (18 per FB)
Set control
Programmable inversion or XOR product term
Up to 5 product terms
Global clock or product-term clock
Reset control
OE control
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9500-series product-term allocator
Share terms from above and below
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9500-series I/O block
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Switch matrix for XC95108

• Could be anything from a limited set of
  multiplexers to a full crossbar.
• Multiplexer -- small, fast, but difficult fitting
• Crossbar -- easy fitting but large and slow

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XC9500 Product Family
9536
9572
95108
95144
95216
95288
Macrocells
36
72
108
144
216
288
Usable Gates
800
1600
2400
3200
4800
6400
tPD (ns)
5
7.5
7.5
7.5
10
10
Registers
36
72
108
144
216
288
Max I/O
34
72
108
133
166
192
VQ44 PC44
PC44 PC84 TQ100 PQ100
PC84 TQ100 PQ100 PQ160
PQ100 PQ160
Packages
HQ208 BG352
PQ160 HQ208 BG352
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CoolRunner-II

• CoolRunner-II Family
• Lowest system cost using advanced features
• Lowest power
• High speed
• Additional security
• Smallest packages
• Including worlds smallest low cost package -
  QF32
• 1.5V, 1.8V, 2.5V 3.3V interface
• 2 to 4 I/O banks

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CoolRunner-II CPLD Architecture
AIM Advanced Interconnect Matrix
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