ECE 667 Student Presentation

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PHDD Multiplicative Power Hybrid Decision
Diagrams1

• ECE 667 Student Presentation
• Gayatri Prabhu
• 1. PHDD An Efficient Graph Representation for
  Floating Point Circuit Verification Y. Chen,
  R. Bryant, ICCAD 1997

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Agenda

• Motivation
• Floating point representation
• PHDD construction
• Floating point function through PHDDs
• Benefits
• Conclusion

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Motivation

• BMDs 1, BMDs 1 ,KBMDs 2 and HDDs 3
  inefficient to map Boolean vectors to floating
  point values.
• Output in the form of a word.
• Need some way of incorporating the radix point
• Need rational number (n/d) representation
• Computationally expensive
• Extend BMDs to PHDDs
• Function with domain Boolean space and range
  floating point

1 Bryant,R.E and Chen Y-A. Veri?cation of
arithmetic circuits with binary moment diagrams,
DAC 1995 2 Drechsler R. , Becker,B. and
Ruppertz,S. KBMDs a new data structure for
veri?cation, DATE 1995 3 Clarke, E.M, Fujita
M, Zhao X. Hybrid decision diagrams overcoming
the limitations of MTBDDs and BMDs , ICCAD 1995
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Floating point representation

• Floating point Radix point at an arbitrary
  position
• IEEE 754 notation to store in memory
• Derived from scientific notation
• Eg 123.45 1.2345 x 102
• Number (-1)sign x (Base)exponent x Mantissa
• Sign 0 means positive and 1 means negative
• Base 2

Sign
Exponent
Mantissa
n
m
http//steve.hollasch.net/cgindex/coding/ieeefloat
.html
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Floating point representation

• Mantissa - m bits
• Radix point after first non-zero digit
• Base 2 gt Non zero-digit 1
• Mantissa always in form 1.X Stored mantissa X
• Exponent n bits
• Stored exponent Actual exponent Bias
• Bias to remove negative numbers in the stored
  format
• For n-bit exponent bias 2n-1 -1
• So for n 3 , m 3 Bias 2(3-1) - 1 0.75
  0.11
• Sign0 Stored exponent -13 2 Stored
  mantissa 0b100

5 5.00 x 100 5 5000.0 x 10-3
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Floating point representation

• Number (-1)Sx 2(EX-Bias) 1.X
• Normal form
• Overflow Exponent requires more bits
• Not considered in PHDDs
• Underflow Number too small to represent with
  precision. Eg0.000000000000075
• Need to approximate to zero
• Denormal form (-1)Sx 2(1-Bias) 0.X

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Failure of BMDs to represent floating point
PHDD An Efficient Graph Representation for
Floating Point Circuit Verification Y. Chen,
R. Bryant, ICCAD 1997
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PHDD Construction and manipulation
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PHDD- Introduction

• Multiplicative Power Hybrid Decision Diagrams
• Multiplicative
• Edge weights multiplied with variables
• Power
• Edge weights restricted to powers of a constant
• Hybrid since different decompositions allowed
• Shannon -
• Positive Davio -
• Negative Davio

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Edge weight rules

• Edge weights w which represents cw
• c constant positive
• w can be positive or negative
• Only c2 considered since the effort is directed
  towards floating point arithmetic.
• All edges have weight
• No weights near edgegt w0

Represented function 20 x021 x122 x2
PHDD An Efficient Graph Representation for
Floating Point Circuit Verification Y. Chen,
R. Bryant, ICCAD 1997
11
PHDD reduction rules (1)

• Normalize edge weights
• Atmost one branch has non-zero weight
• Edge weights 0 except for the top one
• Leaf nodes can have only odd integers or 0.

PHDD An Efficient Graph Representation for
Floating Point Circuit Verification Y. Chen,
R. Bryant, ICCAD 1997
12
PHDD reduction rules (2)

• Introduce negation edges
• Increases sharing
• Helpful whenever a sign bit is involved

PHDD An Efficient Graph Representation for
Floating Point Circuit Verification Y. Chen,
R. Bryant, ICCAD 1997
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Making PHDD canonical

• Follow ordering
• Associate decomposition type with variable
• Remove redundancy
• Merge isomorphic sub-graphs
• Normalize edge weights
• Negation edges whenever necessary
• Zero edge of every node is a regular edge
• Negation of leaf 0 is still leaf 0
• Leaves must be non-negative

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BMD vs PHDD

• BMD

• PHDD

• Decomposition
• - Positive Davio
• Edge weight any number
• Weight manipulation - requires GCD computations

• Decomposition Shannon, Positive Davio
  Negative Davio
• Edge weight Powers of 2 (exponents)
• Weight manipulation just addition and
  subtraction

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Representing a function in PHDD
x1, x0 bits of a number gt X x02x1 and f 2X
x1 x0 f
0 0 1
0 1 2
1 0 4
1 1 8
Representation with Shannon decomposition
PHDD An Efficient Graph Representation for
Floating Point Circuit Verification Y. Chen,
R. Bryant, ICCAD 1997
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Conversion from HDD to PHDD
Extract powers of 2
Reduce
Normalize
PHDD An Efficient Graph Representation for
Floating Point Circuit Verification Y. Chen,
R. Bryant, ICCAD 1997
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Manipulating PHDD
Represent cX where X is a number and c2
PHDD An Efficient Graph Representation for
Floating Point Circuit Verification Y. Chen,
R. Bryant, ICCAD 1997
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PHDDs and ARITHMETIC
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Floating point operations

• Break down into sign, exponent and mantissa part
• PHDDs for each part
• Shannon for sign
• Shannon for exponent
• Positive Davio for mantissa
• Combine all the individual parts with an order
• Bias at the top followed by sign, exponent and
  mantissa

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Floating Point Encoding

• Function(-1)Sx 2(EX-Bias) 1.X
• Exponent 2bits, Mantissa 3bits, Bias1

PHDD An Efficient Graph Representation for
Floating Point Circuit Verification Y. Chen,
R. Bryant, ICCAD 1997
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PHDD and floating point encoding
Normal -gt(-1)Sx 2(EX-Bias) 1.X Denormal
-gt(-1)Sx 2(1-Bias) 0.X EX 3 bits X 4
bits B 3
PHDD An Efficient Graph Representation for
Floating Point Circuit Verification Y. Chen,
R. Bryant, ICCAD 1997
22
Applying PHDDs to arithmetic operations

• Represent numbers in a binary encoded form
• Use composition ( APPLY in BDDs) to combine the
  numbers in operations
• Eg Floating point multiplication

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Floating point multiplication
PHDD An Efficient Graph Representation for
Floating Point Circuit Verification Y. Chen,
R. Bryant, ICCAD 1997
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Advantages and disadvantages

• Advantages
• Six times faster than BMDs
• Uses less memory
• Linear complexity for FP multiplication
• Disadvantages
• Edge weights restricted to powers of 2
• Floating point addition complexity exponential
  with exponent size
• Applications
• Floating point circuit verification

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Conclusion

• PHDDs mainly for floating point verification
• Can represent the following functions which map
  Boolean domain to
• Boolean using Shannon decomposition
• Integer using Positive Davio decomposition
• Floating point using Shannon decomposition for
  sign and exponent Positive Davio for Mantissa

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Questions ?