Signal Processing Using Digital Technology

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Signal Processing Using Digital Technology

• Jeremy Barsten
• Jeremy Stockwell
• December 10, 2002
• Advisors
• Dr. Thomas Stewart
• Dr. Vinod Prasad

2
Digital Signal Processor

• Project Description
• Preliminary Work
• Research
• Design
• Standards and Patents
• Goals
• Schedule

3
Project Description

• All purpose digital signal processor using
  FPGA/VHDL and ASIC/VLSI technology.
• Useable for a variety of applications
• Audio and Video
• Cellular Technology
• Adapted depending on the application.

4
Project Description

• High-level Block Diagram
• Input Processed
• Signal Signal

DIGITAL SIGNAL PROCESSOR
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Filter Design

• Manipulating a digital input utilizing
  multipliers and adders.
• Direct Form II realization of an IIR Filter
• X(n)
  w(n) b0 y(n)
• -a1 b1
• -a2 b2 w(n-1)
• w(n-2)

Z-1
Z-1
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Signal Converters

• Each signal will be analog in nature.
• Requires an analog-to-digital converter at the
  input stage and a digital-to-analog converter at
  the output stage.
• Type of converter will be determined later.

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Adder and Multiplier

• Any basic signal processor consists of different
  stages of addition and multiplication.
• A n-bit by n-bit multiplication will take place
  and result in a 2n-bit value.
• This answer will be added to previous values
  stored in a data register (discussed later).

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Adder and Multiplier

• Cellular Multiplication
• a3 a2 a1 a0
• b0
• b1
• b2
• b3
• p7 p6 p5 p4 p3 p2 p1
  p0

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Adder and Multiplier

• For 2s compliment addition and multiplication

2s Complement Block
Cellular Array
2s B L O C K
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Adder and Multiplier

• x(n)-a1w(n-1)
• -a1 -a2
• w(n-1) w(n-2)
• x(n)
• x(n)-a1w(n-1)
• Shows the consecutive steps in the addition,
  multiplication, and data management.

Memory Management
16-Bit Multiplier
16-Bit Multiplier
Memory Management
32-bit Adder/Subtractor
32-bit Adder/Subtractor
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Data Management

• Need to store old calculated values for later
  use.
• Need a shift-and-store type of data management.
• Will deliver the correct data at the appropriate
  time.

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Data Management

• The possibility of overflow exists in the
  addition and multiplication stage.
• For this reason, a truncation circuit is needed
  to control and adjust the value of the
  adder/multiplier circuit.
• Will also use truncation before sending out the
  final signal.

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Preliminary Work

• Investigation of Xilinx compiler.
• Ripple carry adder v. Carry look ahead adder.
• Parallel multiplier v. Serial multiplier.

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Ripple Carry Adder
16-bit ripple carry adder will have 34 gate
delays
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CLA Adder
16-bit CLA adder will have 10 gate delays
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Xilinx Implementation

• Implemented both adders using VHDL.
• Created simple adder in VHDL (abc).
• Compared results to see what type of adder was
  created by the compiler.
• Results

CLA Adder Ripple Adder Simple Adder
Delay 11.05 ns 22.43 ns 11.05ns

• Checked results using FPGA board.

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Multiplier

• Advantages and disadvantages of using a parallel
  multiplier v. a serial multiplier.
• Investigate the feasibility of using a Parallel
  Multiplier.
• Speed v. Area

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Signed Serial Multiplier

• For a signed serial multiplier, it is necessary
  to sign extend.

• For Example (-3 x 5)
• 1101(-3)
• x 0101(5)
• 11111101
• 0000000
• 111101
• 00000
• 11110001(-15)

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Signed Serial Multiplier
A
B
Sign Extension
Shift Register
Shift Register
Adder/Subtractor
Register
Product
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Area v. Speed

• Implemented Serial adder and simple AxB adder in
  VHDL.

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Area v. Delay (serial)
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Area v. Delay (parallel)
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Other Multiplier Options

• It is possible to use a combination of parallel
  and serial multipliers.
• For example it is possible to use two 8-bit
  parallel multipliers in series which will double
  the delay but will save space.

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Standards and Patents

• Searched the Internet for standards and patents
  on digital signal processors.
• Many of the standards were application specific.
• Could not really find specific standards on
  digital signal processors.

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Hardware and Software Programs

• Xilinx Foundation Software
• Leonardo Spectrum
• L-Edit Pro v8.2
• PSpice Circuit Simulation
• Xilinx XC4005ePC84 FPGA Board
• A/D and D/A converters

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Project Goals

• Determine best trade-off between size and speed
  for the adder/multiplier circuit.
• VLSI implementation of a 4-bit adder and
  multiplier.
• Determine the number of bits used in our
  processor to ensure stability.
• Complete data management and truncation block of
  the processor.
• Decide on specific application.

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Project Schedule

• January/February
• Complete adder/multiplier in VHDL and implement
  on the FPGA board.
• Complete VLSI design of adder/multiplier circuit.
• March
• Determine specific application and design the
  appropriate filter.
• April
• Complete data management and truncation block.
• Implement entire design on FPGA board and
  troubleshoot any errors that arise.
• May
• Prepare final presentation and possibly present
  at Student Expo.

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Signal Processing Using Digital Technology

• Jeremy Barsten
• Jeremy Stockwell
• December 10, 2002
• Advisors
• Dr. Thomas Stewart
• Dr. Vinod Prasad