STT-RAM Feasibility Study

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STT-RAM Feasibility Study

• Amr Amin
• UCLA
• Jan 2010

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Outline

• Introduction
• Memory Cell
• Cell Area Calculation
• Write Current Limitations
• Reading Techniques and Limitations
• Effect of Process Variations and Mismatch
• MTJ Feasible Region
• Area Minimization

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Introduction

• The need for a universal memory
• Brief history of magnetic device memories
• Description of the MTJ device
• Literature survey
• Summary of the paper flow

4
STT-RAM Cell

• Schematic diagram
• Anti-parallelizing / Parallelizing currents
• Read disturb problem
• Cell layout
• Basic cell area vs. access device width

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Effective Cell Area

• This takes into account the overhead of
• Column MUX
• Row decoder
• Sense Amp
• I/O circuits
• Area optimization should also consider
• Optimum memory partitioning
• Access transistor vs. column MUX areas

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Write Current Limitations

• MOS drain current equation and fitting
• Maximum allowed RP and RAP for certain write
  current(s)
• Column MUX design (justification for using
  T-gates instead of P-transistors)
• Effect of each of the four MUX devices on the
  maximum allowed resistances

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NMOS Drain Current
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PMOS Drain Current
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Maximum RAP
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Maximum RP
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Reading Limitations

• Current sensing
• Voltage sensing

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Constant Read Signal Contours

• Current Sensing

• Voltage Sensing

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Process Variations

• MOS variations
• Min K and max VT
• Reduce the maximum allowed RP and RAP
• Mismatch
• Degrades sensitivity of the SA
• Higher nominal read margin is required
• MTJ variations
• MgO thickness and area variations
• Distort the nominal feasible region of the MTJ

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Process Variations
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MTJ Feasible Region

• What is the MTJ feasible region in the RPRAP
  plan given the following
• Desired write current
• Desired basic cell area
• Column MUX width
• Certain technology
• Certain variations (Yield)
• Matching parameters (Yield)

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Dec-2009 Tape-out

• IBM-90nm-CMOS
• VWL VDD 1 V
• IWR 500 µA
• Wa2.56 µm
• WP,MUX16 µm
• WN,MUX8 µm
• MOS K varies /- 20
• MOS VT varies /- 50mV
• MTJ RA 2 O.µm2
• MTJ KRA 34 O.µm2/nm
• MTJ TMR 100
• MTJ KTMR 200 /nm
• MTJ ?tMgO 0.2 Ao
• Current Sensing VR 600 mV
• Current Sensing ?IR 20 µA

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SRAM-Area Constraint

• IBM-90nm-CMOS
• VWL VDD 1 V
• IWR 500 µA
• Wa2.56 µm
• WP,MUX16 µm
• WN,MUX8 µm
• MOS K varies /- 20
• MOS VT varies /- 50mV
• MTJ RA 2 O.µm2
• MTJ KRA 34 O.µm2/nm
• MTJ TMR 100
• MTJ KTMR 200 /nm
• MTJ ?tMgO 0.2 Ao
• Current Sensing VR 600 mV
• Current Sensing ?IR 20 µA

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Flash-Area Constraint
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DRAM-Area Constraint
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Area Minimization Problem

• Minimize Effective cell area
• Subject to
• MTJ resistances and write current value
• MTJ variations
• Parallelizing/Anti-parallelizing Write current
  equations
• MOS variations and matching parameters
• Speed must come into picture to constrain the
  optimum memory partitioning
• May be able to formulate this into a standard
  optimization problem form that can be solved
  efficiently

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Remaining Issues

• Analyzing Read/Write Speed and adding this as a
  constraint in the optimization problem
• The same with power
• More analysis is needed for the minimum required
  sensing signal (current or voltage)
• CMOS mismatches and offset
• Signal degradation due to MgO thickness variation
• Possible signal degradation due to CMOS process
  variation (dependant on the SA implementation)
• Regenerating all results for different
  technologies