80GHz Modulator Designs

1
80GHz Modulator Designs

• Ian Harrison
• School of Electrical and Electronic Engineering
• University of Nottingham
• UK
• Work done at
• Department of ECE
• University of California, Santa Barbara
• USA

Special thanks PK, Zak, Mattias for fabrication
of circuits and devices Miguel for advice Paidi
and Navin for cricket discussions Mark Rodwell
for useful discussion and use of infrastructure
Harrison_at_ece.ucsb.edu 805-893-8044,
805-893-3262 fax
2
Introduction

• Concentrate on more recent work
• Thermal Modelling
• Modulator work
• design issues
• Simulation results

3
Design Specifications

• Two types of optical modulator
• LiNb03 Mach Zehnder -Interference
• Split beam into 2, induce 0 or 180 phase shift
• Large driving voltage eg 10GBits 5Vpp
• Electroabsorption
• Quantum confined stark effect
• Smaller driving voltage eg 10GBits 3Vpp
• Design specifications

E0
E?0
E0
EA modulator 2V , 50 Ohm input Output should be
matched
Attn
E?0
?
4
How do we get speed improvement

• Switching speed limited by output capacitance

Design Specifications set ?V and RL ? sets I
Formula simplistic ?insight
Reduce C by decreasing AC ? Increase in J since
I fixed ? J limited by Kirk Effect ? Increase
in J increase dissipated power density
5
Kirk effect and switching time

• Above Jkirk massive increase in base charge
• ? Base push out (Field Screening)

Vsat3.5 105cms-1
?VCE
Predicts straight line

• Wide emitter, narrow base mesa
• Rb limits the emitter width

6
Why is thermal management important?

• As J increases so does the power density. This
  will lead to an increase in the temperature.

TC JKirk Le
Å mAµm-2 µm
3000 1.0 81
2000 2.3 34
1500 4.1 19
1000 9.8 8.6
For VCE1V ? PD10.6mWµm-3
For VCE1V ? PD98mWµm-3!!
7
Thermal Modeling of HBT (1)

• 3D Finite Element using Ansys 5.7
• K (Thermal conductivity) depends temperature
• K depends on doping
• For GaAs heavily doped GaAs 65 less than undoped
  GaAs
• Unknown for InP or InGaAs use GaAs dependency

? Large uncertainty in values
Material K300 n K300(exp) Refs
InP 0.68 1.42 0.68-0.877 1
InGaAs 0.048 1.375 0.048-0.061 2
Au 3.17 - 3
J.C.Brice in Properties of Indium phosphide
eds S Adachi and J.Brice pubs INSPEC London
p20-21 S Adachi in Properties of Latticed
Matched and strained Indium Gallium Arsenide ed
P Bhattacharya pubs INSPEC London p34-39 CRC
Materials science and engineering handbook, 2nd
edition ,eds J.F Shackelford,A.Alexander, and J.S
Park, pubs CRC press, Boca Raton, p270
8
Layout used for simulation validation
Actual device

• Need simplified model for simulation
• ? reduce simulation time and storage requirements
• Ignore base pad collector interconnect
• 2 orthogonal symmetry lines
• Simulate only ¼ device

Layer structure Layer structure
Emitter 0.04µm n InGaAs 0.12 µm n- InP
Base 0.03 µm p InGaAs
Collector Setback Grade Drift 0.02 µm InGaAs 0.024 µm Grade 0.156 µm InP
Subcollector Etchstop 0.050 µm n InGaAs 0.200 µm n InP
Substrate 500 µm Fe InP
Polyimide for passivation Very low K ignore In
thermal analysis
After M. Dahlstrom
Simulated ¼ Device
9
Validation of Model
Caused by Low K of InGaAs
Max T in Collector
Advice Limit InGaAs Increase size of
emitter arm
Ave Tj (Base-Emitter) 26.20C Measured
Tj26C Good agreement.
10
Effect of decreasing collector thickness
Assumptions Devices thermally isolated Device
structure identical to validation
structure Perfect switching waveform Observation
s Temperature increases rapidly for thin
collectors (?Tmax 60C for TC1000Å) Collector
temperature always higher than Tj
(?TMax-?Tj)gt30C ) Increase in ISC? possible
failure mechanism ( Major failure problem in GaAs
HBTs) Temperature of one device approximately
double when circuit is not switching
Choose Le For JJKirk We0.5um
50 duty cycle
11
Analysis of 40,80,160 Gbit/s devices

• To obtain speed inprovements require to scale
  other device parameters.

Speed (Gbit/s) 40 80 160
Collector Thickness (Å) 3000 2000 1000
Base Sheet resistance (??) 750 700 700
Base contact resistance (?-?m2) 150 20 10
Base Thickness (Å) 400 300 250
Base Mesa width ( ?m) 3 1.6 0.4
Current Density (mA/?m2) 1 2.3 9.8
Emitter. Junction Width ( ?m) 1 0.8 0.2
Emitter Parasitic resistivity (?-?m2) 50 20 5
Emitter Length ( ?m) 6 3.3 3.2
Predicted MS-DFF (GHz) 62 125 237
Ft (GHz) 170 260 500
Fmax (GHz) 170 440 1000
Tj (K) 7.5 14 28
TMax (K) 10 20 49
TMax (No Etch Stop layer) (K) 7.5 13 21
Reduction of parasitic CBC
Conservative 1.5x bit rate
When not switching values will double
Device parameters after Rodwell et al
12
Thermal Analysis using ADS
R network easily solved Using ADS

• For simulations need a model that can be solved
  by ADS so that thermal and circuit simulations
  can be coupled.
• Thermal generation ? current source
• Thermal resistance ? resistors
• Thermal capacity ? capacitors (If static not
  needed)
• Temperature variation of thermal conductivity
  not modelled because resistors do not depend on
  current (This restriction could be lifted)

13
Coupled Circuit-Thermal modelling
Ambient T

• How do the advance device models do it?
• Device at one temperature
• Devices thermally isolated and described by a
  single resistance
• Thermal circuit hidden from user
• How do we want to do it
• Access to thermal circuit
• ß only slightly temperature dependent
• Large change in VBE(ON)

Value used in model
Temperate rise
Power dissipated in the device
Thermal Resistance
My model

• ? is the band gap shrinkage factor
• Not usually given but optical measurements on
  band gap ( Optical values must be used with
  caution )
• 0.0004 for both InP and InGaAs

14
Can we measure Rth (Method of Lui et al )
Ramp IB for different VCE Measure VBE and IC
Large uncertainty in values. Fitting regression
curves helps to reduce error
Depends on current density
15
An alternative method for finding RT
IC fixed , sweep VB

• Obtain RT (Pave)
• Changes in VC larger more accurate
• RT measured at lower Pave
• Thermal instability possible
• Need to be careful on the VB range

Ic 6mA,6mA Ic12mA,12mA
From gradient ?RT
Ic 6mA,6mA Ic12mA,12mA
16
Comparison of the two methods
Emitter Mask 12 x 0.7 mesa width 1.7
New method
Classic Method
Linear interpolation.

• Classic method badly affected by the 4145
  resolution.
• Better measurements at very high power. Often
  leads to device failures
• Problems with every fourth measurement of 4145 in
  new method
• Need to compare the two methods using the
• 4155

Empirical Curve fit
17
Which model to estimate Rth
Model 1

• Finite elements clearly shows diffusion of heat
  along the collector under the base contacts.
• Rth should depend on base mesa size
• Model 1
• ? Models flow of heat under base
• ? Thermal circuit complex
• Model 2
• ? Thermal circuit simple
• ? Over estimates RT
• Both Models
• ? Both will underestimate RT at high powers
• Experimental results

Model 2
Mesa Width
RT(C/W) 1.7 2.1 2.7
4 5500 5100 6200
12 1800 1800
Length
? Use Model 2
18
Thermal resistance calculations

• Thermal resistance of layers can be estimated
  from the thermal conductivity if no heat
  spreading is assumed.
• The emitter interconnect acts as a thermal link
• The thermal resistance of the substrate is
  estimate by solving the 3D heat flow problem
  using separable variables technique. This is the
  same method Lui et al used to calculate RT of
  single and multi-finger HBT power transistors.

Mesa Width
RT(C/W) 1.7 2.1 2.7 Theory
4 5500 5100 6200 5700
12 1800 1800 2071
Length
After M. Dahlstrom
Spreadsheet ThermalCalc.xls
19
Stability of single BJTs (Intro)

• Well known problem solved by ballasting with
  emitter or base resistance.
• Known to be a problem in power amplifiers.
• May argue, incorrectly, that in digital circuits
  this is not a problem because we are driving the
  circuits with a constant current source.
• Need to know how large we can make the emitters
  before hot spots form and current hogging
  becomes an issue.

X
If the transistor base is being driven with a
constant voltage. The collector current will
increase until it gets to point X. Any further
increase in base voltage will cause an infinite
increase in the collector current resulting in
physical damage to the device.
20
Single Emitter Stability
Caused by the increase in RT when device size is
reduced.
Uncertainty in Re
Caused by the reduction of Re with length
J 1 ? 5mAµm-2
?E60O from DC measurements
Optimum operating point
21
Hot spot formation (not finished)
Device broken into sections
Thermal model of substrate
Base electrical resistance

• Need to do
• Simulate DC measurements
• Compare with measurements

Thermal resistance of the emitter connection
22
Modulator design (Matching)
Passive ? simple ? high bias current All
active circuits ?Bias current lower ? need to
prevent saturation Resistive feedback ?No
flexibility Zo1/gm Feedback Zo1/(gmß) but
additional EF more ringing
Passive
Resistive Feedback
Feedback
RC
Feedback ßlt1
23
Effect of current source design on output
Current switch (only one half)
Capacitive coupling to Control line reduces
output resistance
Vo
Vm
Vi
Common Reference
Different Reference
Vo
Vm
Vi
Use resistor- inefficient power use, but simple
24
Output stage options
Performance depends on the quality of the ground
Bias generated by diode
Miller effect increases output cap
With diode base
Ideal Vsrc
25
Current designs

• 2 and 3 stage amplifiers
• Cascode and simple output

3 stage cascode output
80GBit/s
160GBit/s
Simulations show that 160GBit is just possible
with 1500A collector.
26
What to do in the future

• Fabricate and test the current design
• Design amplifiers with output voltage
• Simulate with self heating
• Investigate the more advanced BJT models

27
Conclusion

• 160 Gbits Modulator has been designed
• Electro -thermal model has been developed which
  can be simulated using ADS
• What would I change if I could rewind the clock
• Gone in the clean room.